SABRE-LL-I datasheet(108/141 Pages) STMICROELECTRONICS

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GPIO pins

SABRE-LL-I

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This bit is at logic level “1” if AUX1 regulator is a system regulator but its power stage is externally realized

(and therefore the regulation loop is not used to drive bridge 3). In this case Vloop1IsSys bit will be at logic

level “1”, while Vloop1OnMtr3SideA and Vloop1OnMtr3SideB bits will be at logic level “0” in

CoreConfigReg register.

In all configurations in which GPIO[5] is enabled as output:

a) the GPIO[5] pin can be always used as an analog input to the ADC system (ADC function) by writing its

address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;

b) the GPIO[5] pin can be always used as a digital input so its value can be always read through SPI

interface (SPI_IN function);

the GPIO[5] pin is a rail to rail, back to back output supplied by V3v3.

Table 80.

GPIO[5] specification

Parameter

Description

Test condition

Min

Typ

Max

Unit

VIH

High level input voltage

1.6

VIL

Low level input voltage

0.8

VHYS

Input voltage hysteresis

0.22

VOL

Low level output voltage

IOUT = 15mA

0.4

VOH

High level output voltage

IOUT = 5mA

2.75

ILEAKAGE

Leakage current

≤V

out ≤ V3v3

-1

µA

tDELAY

Delay from serial write to pin low

CLOAD =50 pF

(1)

Measured between nSS rising edge and 50% of Vout.

500

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