ACS8526P datasheet(5/74 Pages) SEMTECH

5 / 74 page

ADVANCED COMMUNICATIONS

FINAL

DATASHEET

Revision 4.01/June 2006 © Semtech Corp.

Page 5

www.semtech.com

ACS8526 LC/P LITE

MFrSync

TTL/CMOS

Output Reference: 2 kHz Multi-Frame Sync output.

19,

O1POS,

O1NEG

LVDS/PECL

Output Reference 1: Differential output., default LVDS.

IP_FREQ0

TTLD

Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.

SEC1

TTLD

Input Reference 1: Primary input.

SEC2

TTLD

Input Reference 2: Secondary input.

IP_FREQ1

TTLD

Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.

IP_FREQ2

TTLD

Input Reference Frequency Select: Frequency select for input SEC1 and SEC2.

O2_FREQ0

TTLD

Output O2 Frequency Select: Frequency select for output O2.

O2_FREQ2

TTLD

Output O2 Frequency Select: Frequency select for output O2.

TRST

TTLD

JTAG Control Reset Input: TRST = 1 to enable JTAG Boundary Scan mode.

TRST = 0 for normal device operation (JTAG logic transparent). NC if not used.

O2_FREQ1

TTLD

Output O2 Frequency Select: Frequency select for output O2.

TMS

TTLD

JTAG Test Mode Select: Boundary Scan enable. Sampled on rising edge of TCK.

NC if not used.

CLKE

TTLD

SCLK Edge Select: SCLK active edge select, CLKE = 1, selects falling edge of

SCLK to be active.

SDI

TTLD

Interface Address: SPI compatible Serial Data Input.

CSB

TTLU

Chip Select (Active Low): This pin is asserted Low by the external device

(microprocessor) to enable the Serial interface.

O1_FREQ0

TTLU

Output O1 Frequency Select: Frequency select for output O1.

O1_FREQ1

TTLU

Output O1 Frequency Select: Frequency select for output O1.

SCLK

TTLD

Serial Data Clock: The Low to High transition on this input latches the data on the

SDI input into the internal registers. The active clock edge (defined by CLKE)

latches the data out of the internal registers onto the SDO output.

PORB

TTLU

Power-On Reset: Master reset. If PORB is forced Low, all internal states are reset

back to default values.

TCK

TTLD

JTAG Clock: Boundary Scan clock input.

TDO

TTL/CMOS

JTAG Output: Serial test data output. Updated on falling edge of TCK.

TDI

TTLD

JTAG Input: Serial test data Input. Sampled on rising edge of TCK. NC if not used.

SDO

TTLD

Interface Address: SPI compatible Serial Data Output.

TTL/CMOS

Output Reference: Programmable, default 19.44 MHz.

O1_FREQ2

TTLU

Output O1 Frequency Select: Frequency select for output O1.

SONSDHB

TTLD

SONET or SDH frequency select: Sets the initial power-up state (or state after a

PORB) of the SONET/SDH frequency selection registers, Reg. 34, Bit 2 and

Reg. 38, Bit 5, Bit 6 and Reg. 64 Bit 4. The register states can be changed after

power-up by software. When set Low, SDH rates are selected (2.048 MHz etc.)

and when set High, SONET rates are selected (1.544 MHz etc.) The register

states can be changed after power-up by software.

Table 3 Other Pins (cont...)

Pin Number

Symbol

I/O

Type

Description

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