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Low-Voltage Inhibit (LVI)

Data Sheet

MC68HC908RF2 — Rev. 4.0

104

Low-Voltage Inhibit (LVI)

MOTOROLA

In addition to forcing a reset condition, the LVI module has a second circuit

dedicated to low-voltage detection. When VDD falls below VLVS, the output of the

low-voltage comparator asserts the LOWV flag in the LVI status register (LVISR).

In applications that require detecting low batteries, software can monitor by polling

the LOWV bit.

8.3.1 False Trip Protection

The VDD pin level is digitally filtered to reduce false dead battery detection due to

power supply noise. For the LVI module to reset due to a low-power supply, VDD

must remain at or below the VLVR level for a minimum 32–40 CGMXCLK cycles.

See Table 8-1.

8.3.2 Short Stop Recovery Option

The LVI has an enable time of tEN. The system stabilization time for power-on reset

and long stop recovery (both 4096 CGMXCLK cycles) gives a delay longer than the

LVI enable time for these startup scenarios. There is no period where the MCU is

not protected from a low-power condition. However, when using the short stop

recovery configuration option, the 32 CGMXCLK delay must be greater than the

LVI turn on time to avoid a period in startup where the LVI is not protecting the

MCU.

NOTE:

The LVI is enabled automatically after reset or stop recovery, if the LVISTOP of the

CONFIG register is set. (See Section 3. Configuration Register (CONFIG).)

Table 8-1. LOWV Bit Indication

VDD

Result

At Level:

For Number of CGMXCLK Cycles:

VDD > VLVR

ANY

Filter counter remains clear

VDD < VLVR

< 32 CGMXCLK cycles

No reset, continue counting CGMXCLK

VDD < VLVR

Between 32 and 40

CGMXCLK cycles

LVI may generate a reset

after 32 CGMXCLK cycles

VDD < VLVR

> 40 CGMXCLK cycles

LVI is guaranteed to generate

a reset

Freescale Semiconductor, Inc.

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