TLC5910

LED DRIVER

SLLS392 – NOVEMBER 1999

7

POST OFFICE BOX 655303

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

OUT0–DOUT15

2,3,5,6,8,9,11,12,

14,15,17,18,20,21,

23,24

O

Constant current output

PDOUT

70

I/O

Resistor connection for PLL feedback adjustment

RBIAS

74

I/O

Resistor connection for PLL oscillation frequency setting

RSEL0

RSEL1

60

59

I

Input/output port selection and shift register data latch switching.

When RSEL1 is low and RSEL0 is low, the gray scale data shift register latch is selected

to port A and the dot correction register latch is selected to port B.

When RSEL1 is low and RSEL0 is high, the brightness control register latch is selected to

port A and the dot correction register latch is selected to port B.

When RSEL1 is high and RSEL0 is low, the dot correction register latch is selected to port

A and no register latch is selected to port B.

TEST1–TEST4

29,97,99,100

I

TEST. Factory test terminal. These terminals should be connected to GND.

THERMAL PAD

package bottom

Heat sink pad. This pad is connected to the lowest potential IC or thermal layer.

TSENA

31

I

TSD(thermal shutdown) enable. When TSENA is high, TSD is enabled. When TSENA is

low, TSD is disabled.

VCOIN

75

I/O

Capacitance connection for PLL feedback adjustment

VCCANA

33

Analog power supply voltage

VCCLOG

93

Logic power supply voltage

VCCIF

92

Interface power supply voltage

VCCLED

26

LED driver power supply voltage

WDTRG

56

I

WDT (watchdog timer) trigger input. By applying a scan signal to this terminal, the scan

signal can be monitored by turning the constant current output off and protecting the LED

from damage when the scan signal stopped during the constant period designed.

WDCAP

30

I/O

WDT detection time adjustment. WDT detection time is adjusted by connecting a capacitor

between WDCAP and GND. When WDCAP is directly connected to GND, WDT function

is disabled. In this case, WDTRG should be tied to a high or low level.

XDCLAT

61

I

Data latch for dot correction. When XDCLAT is high, data on the shift register for dot

correction data from DCDIN (port B) goes through latch. When XDCLAT is low, data is

latched. Accordingly, if data on the shift register is changed during XDCLAT high, this new

value is latched (level latch).

XDOWN1

55

O

Shutdown. XDOWN1 is configured as an open collector. It goes low when constant current

output is shut down by WDT or TSD function.

XDOWN2

54

O

LED disconnection detection output. XDOWN2 is configured as an open collector.

XDOWN2 goes low when an LED disconnection is detected.

XDWN2TST

27

I

Test for XDOWN2. When XDWN2TST is low, XDOWN2 goes low. (This terminal is internally

pulled up with 50 k

Ω)

XENABLE

66

I

DCLK enable. When XENABLE is low, data transfer is enabled. Data transfer starts on the

valid edge of DCLK after XENABLE goes low. During XENABLE high, no data is transferred.

XGSOUT

52

O

Clock output for gray scale. When MAG0 to MAG2 are all low, the clock with GSCLK inverted

appears on this terminal. When either MAG is not low, PLLCLK appears on this terminal.

XLATCH

63

I

Latch. When XLATCH is high, data on the shift register from DIN (port A) goes through latch.

When XLATCH is low, data is latched. Accordingly, if data on the shift register is changed

during XLATCH high, this new value is latched (level latch).

XOE

65

I

Data output enable. When XOE is low, DOUT0–9 terminals are driven. When XOE is high,

DOUT0–9 terminals go to a high

XPOUT

51

O

GSPOL output inverted

XRST

34

I

Blank (Light off). When XRST is low, all the output of the constant current driver is turned

off. (This terminal is internally pulled up with 50 k

Ω)