TLC5910

LED DRIVER

SLLS392 – NOVEMBER 1999

17

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

output current adjustment on each constant current output – LED brightness adjustment

By using the 6 bits of the dot correction latch, the output current on each constant current output can be adjusted

to 64 steps. 1 step of 0.8% current ratio between 100% and 50.8% when the set output current is 100% by an

external resistor at 111111h of the latched value and the lower 6 bits of the brightness control register. By using

this function, the brightness deviation due to LED brightness variation can be minimized. When DCENA is pulled

low, the output current is set to 100% without dot correction.

Table 4. Relative Current Ratio By Constant Current Output

CODE

CURRENT RATIO (%)

IOLC=40 (mA)

MSB 000000 LSB

50.8

20.3

.

.

.

.

.

.

.

.

.

.

.

.

111110

99.2

39.7

111111†

100

40

† DCENA is low.

clock edge selection

The high speed clock signal is delayed due to the duty ratio change through multiple stages of an IC or through

the module stages shown in Figure 6.

A’

IN

A

OUT

IN

A

OUT

OUT’

IN

A

OUT

IN’

A’

OUT

a) Propagate through multiple stages buffer

with slow falling edge

b) Insert inverter between buffers

Figure 6. Clock Edge Selection

As shown in Figure 6 a), if the falling at the internal buffer is behind the rising, the clock will disappear as multiple

cascade connections are made. To resolve this problem, the duty ratio can be held unchanged using the

connection as shown in Figure 6 b) if the valid clock edge can be selected (arrow in Figure 6). Note that the clock

delay is not avoided even in this case.

The device incorporates the clock edge selection function for each DCLK and GSCLK. By using this function,

the falling edge or rising edge for the valid edge can be selected depending on the status of DPOL and GSPOL.

Thus the degradation for the duty ratio can be reduced. The relation between each signals is shown in

Table 5.