TLC5910

LED DRIVER

SLLS392 – NOVEMBER 1999

15

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

(6 bits)

OUT15

Data

XLATCH

(6 bits)

OUT14

Data

(6 bits)

OUT1

Data

(6 bits)

OUT0

Data

Latch for Dot Correction

16th byte

DCDIN5 MSB

DCDIN0 LSB

DCDOUT0 to 5

Shift Register for Dot Correction

15th byte

DCDIN5 MSB

DCDIN0 LSB

2nd byte

DCDIN5 MSB

DCDIN0 LSB

1st byte

DCDIN5 MSB

DCDIN0 LSB

DCDIN0 to 5

DCCLK

Using Port B (RSEL0=L or H, RSEL1=L)

(6 bits)

OUT15

Data

XLATCH

(6 bits)

OUT14

Data

(6 bits)

OUT1

Data

(6 bits)

OUT0

Data

Latch for Dot Correction

16th byte

DCDIN5 MSB

DCDIN0 LSB

DOUT0 to 5

Shift Register for Dot Correction

15th byte

DCDIN5 MSB

DCDIN0 LSB

2nd byte

DCDIN5 MSB

DCDIN0 LSB

1st byte

DCDIN5 MSB

DCDIN0 LSB

DIN0 to 5

DCLK

Using Port A (RSEL0=L, RSEL1=H)

Figure 5. Relationship Between Shift Register and Latch for Dot Correction

write data to shift register latch

The shift register latch written to is selected using the RSEL0 and RSEL1 terminals. At port A, the data is applied

to the DIN data input terminal and clocked into the shift register synchronizing to the rising edge of DCLK after

XENABLE is pulled low. At port B, the data is applied to the DCDIN data input terminal and clocked into the

shift register synchronizing to the rising edge of DCCLK. The shift register for the gray scale data is configured

with 16

× 10 bits and the shift register for dot correction is configured with 16 x 6 bits resulting in sixteen times

DCLK, and the shift register for brightness control is configured with 1 x 10 bits resulting in one times DCLK.

At number of DCLK input for each case, data can be written into the shift register. In this condition, when

XLATCH at port A or XDCLAT at port B is pulled high, data in the shift register is clocked into latch (data through),

and when XLATCH at port A or XDCLAT at port B is pulled low, data is held (latch).