tsu (RSEL–DOUT)

Default Value “0”

(Brightness Control Latch: Internal Signal)

D0_F

D0_A

D0_C

D9_C

D9_J

D9_K

D9_L

D9_M

D9_N

D9_O

D9_B

RSEL0

BCENA

XOE

DCLK

XLATCH

DOUT0

DOUT9

th (XLATCH–DCLK)

Figure 13. Timing Diagram (Shift Register for Brightness Control)

BCL_0–5

twh (XLATCH)

D0_E

D0_G

D0_H

D0_I

td (DCLK–DOUT)

td (XOE↑–DOUT)

RSEL1

DIN0

DIN9

BCL_6–9

XENABLE

tsu (RSEL–DCLK)

Default Value “1”

tsu (RSEL–XLATCH)

th (RSEL–XLATCH)

tsu (RSEL–DCLK)

D0_A

D0_C

D0_J

D0_K

D0_L

D0_M

D0_N

D0_O

D0_B

Default Value “1”

Default Value “0”

D<5:0>_A

D<9:6>_A

D9_F

D9_A

D9_C

D9_E

D9_G

D9_H

D9_I

DPOL and DCLK can be replaced with signals inverted with each other. Same as the shift register for the gray scale data.

DPOL

D9_A

td (XOE↓–DOUT)

Hi-Z

Hi-Z