TLC5910

LED DRIVER

SLLS392 – NOVEMBER 1999

14

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

(10 bits)

OUT15

Data

XLATCH

(10 bits)

OUT14

Data

(10 bits)

OUT1

Data

(10 bits)

OUT0

Data

Latch for Gray Scale Data

16th byte

DIN9 MSB

DIN0 LSB

DOUT0 to 9

Shift Register for Gray Scale Data

15th byte

DIN9 MSB

DIN0 LSB

2nd byte

DIN9 MSB

DIN0 LSB

1st byte

DIN9 MSB

DIN0 LSB

DIN0 to 9

DCLK

Figure 3. Relationship Between Shift Register and Latch for Gray Scale Data

shift register latch for brightness control

The shift register latch for brightness control is configured with 1

× 10 bits. Using the shift register latch for

brightness control, the division ratio of the gray scale clock can be set and the output current value on constant

current output can be adjusted. When powered up, the latch data is indeterminate and the shift register is not

initialized. Data should be written to the shift register latch prior to lighting-on (BLANK=L) when these functions

are used. Also, the latch value for brightness control cannot be rewritten when the constant current output is

turned on. When these functions are not used, the latch value can be set to the default value setting BCENA

to low level (connect to GND). Also, DIN9 is assigned to the LSB of the reference current control to maintain

the compatibility with TLC5901/02/03 family. The configuration of the shift register and the latch for brightness

control is shown below.

XLATCH

Latch for Brightness Control

DOUT0 to 9

DIN0 to 9

DCLK

Current Data Adjusted On Constant Current Output

00

11

1

1

MSB

LSB

MSB

LSB

Shift Register for Brightness Control

DIN8

DATA

DIN7

DATA

DIN6

DATA

DIN4

DATA

DIN3

DATA

DIN2

DATA

DIN1

DATA

DIN0

DATA

(Note A)

Gray Scale Clock Division Ratio Data Set

Note A: Indicates default value at BCENA low.

00

11

DIN5

DATA

DIN9

DATA

Figure 4. Relationship Between Shift Register and Latch for Brightness Control

shift register latch for dot correction

The shift register latch for dot correction is configured with 16

× 6 bits. Using the shift register latch for dot

correction, the current value on the constant current output can be set individually. When powered up, the latch

data is indeterminate and the shift register is not initialized. Data should be written to the shift register latch prior

to lighting-on (BLANK=L) when these functions are used. Also, the latch value for dot correction cannot be

rewritten when the constant current output is turned on. When these functions are not used, the latch value can

be set to the default value setting of DCENA to low level (connect to GND). The configuration of the shift register

and the latch for dot correction is shown in Figure 5.