Hi-Z

..

.

RSEL1

RSEL0

XOE

DIN0

DCLK

DIN9

XLATCH

DOUT0

DOUT5

XENABLE

twh (XLATCH)

td (XOE↑–DOUT)

Figure 15. Timing Diagram (Shift Register for Dot Correction : Using Port A)

DPOL

DCDOUT0

D0_A

D0_C

D0_J

D0_K

D0_L

D0_M

D0_N

D0_O

D9_C

D9_J

D9_K

D9_L

D9_M

D9_N

D9_O

D9_A

D0_F

D0_A

D0_C

D0_E

D0_G

D0_H

D0_I

Hi-Z

D5_F

D5_A

D5_C

D5_E

D5_G

D5_H

D5_I

Hi-Z

DCDOUT5

DOUT

<9:6>

tsu (RSEL–XLATCH)

tsu (RSEL–DCLK)

td (XOE↓–DOUT)

tsu (RSEL–DOUT)

td (DCLK–DCDOUT)

th (XLATCH–DCLK)

td (DCLK–DOUT)

tsu (RSEL–DCLK)

DPOL and DCLK can be replaced with signals inverted with each other. Same as the shift register for the gray scale data.

..

.

D0_F

D0_A

D0_C

D0_E

D0_G

D0_H

D0_I

D5_F

D5_A

D5_C

D5_E

D5_G

D5_H

D5_I

D0_B

D9_B

th (RSEL–XLATCH)

td (XOE↓–DOUT)