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TLC5910PZP Datasheet(PDF) 26 Page - Texas Instruments |
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TLC5910PZP Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 30 page  th (RSEL–XDCLAT) tsu (RSEL–DCCLK) RSEL1 RSEL0 tsu(XENABLE–DCLK) DCDIN0 DCCLK DCDIN5 XDCLAT DCDOUT0 DCDOUT5 twh (XDCLAT) Figure 14. Timing Diagram (Shift Register for Dot Correction : Using Port B) DCENA D5_C D5_J D5_K D5_L D5_M D5_N D5_O D5_B D0_C D0_J D0_K D0_L D0_M D0_N D0_O D0_B tsu(RSEL–DCCLK) th (XDCLAT–DCCLK) td (DCCLK–DCDOUT) D5_F D5_A D5_C D5_E D5_G D5_H D5_I DCL_0–15 Default Value “1” (Dot Correction Latch: Internal Signal: 6 bit x 16) Default Value “1” Dx<15:0>_A (Note) tsu (RSEL–XDCLAT) D0_A D5_A D0_F D0_A D0_C D0_E D0_G D0_H D0_I NOTE: Register value is immediately before DCLAT ↓. |
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