TMS320VC5504 datasheet(69/128 Pages) TI

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6.5.3

Clock PLL Electrical Data/Timing (Input and Output Clocks)

CLKIN

TMS320VC5504

Fixed-Point Digital Signal Processor

www.ti.com

SPRS609A – JUNE 2009 – REVISED JULY 2009

Table 6-3. Timing Requirements for CLKIN(1)(2)(3) (see Figure 6-7)

CVDD = 1.05 V

CVDD = 1.3 V

NO.

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

88.577,

Cycle time, external

83.333,

tc(CLKIN)

clock driven on

16.67

CLKIN

81.380

Pulse width, CLKIN

tw(CLKINH)

0.466 * tc(CLKIN)

high

Pulse width, CLKIN

tw(CLKINL)

0.466 * tc(CLKIN)

low

Transition time,

tt(CLKIN)

0.34 * tc(CLKIN)

CLKIN

(1)

The CLKIN frequency and PLL multiply factor should be chosen such that the resulting clock frequency is within the specific range for

CPU operating frequency.

(2)

The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

(3)

For more details on the PLL multiplier factors, see the TMS320VC5505 DSP System User's Guide (Literature Number SPRUFP0).

Figure 6-7. CLKIN Timing

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