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MB91F613 Datasheet(PDF) 84 Page - fujitsu semiconductor |
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MB91F613 Datasheet(HTML) 84 Page - fujitsu semiconductor |
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84 / 104 page  MB91610 Series 84 DS07-16907-2E (10) I2C Timing (VCC = AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V, Ta = − 40 °C to + 85 °C) *1 : R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2 : The maximum tHDDAT must satisfy that it doesn't extend at least “L” period (tLOW) of device's SCL signal. *3 : A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device satisfies the requirement of “tSUDAT ≥ 250 ns”. *4 : tCYCP is the peripheral clock cycle time. To use I2C, set the peripheral bus clock at 8 MHz or more. Parameter Symbol Pin name Condi- tions Typical mode High-speed mode*3 Unit Min Max Min Max SCL clock frequency fSCL SCKn (SCLn) CL = 50 pF, R = (Vp/IOL) *1 01000400 kHz “(Repeated) START condition” hold time SDA ↓ → SCL ↓ tHDSTA SOUTn (SDAn) SCKn (SCLn) 4.0 ⎯ 0.6 ⎯μs SCL clock “L” width tLOW SCKn (SCLn) 4.7 ⎯ 1.3 ⎯μs SCL clock “H” width tHIGH SCKn (SCLn) 4.0 ⎯ 0.6 ⎯μs “Repeated START condition” setup time SCL ↑→ SDA ↓ tSUSTA SCKn (SCLn) 4.7 ⎯ 0.6 ⎯μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDAT SOUTn (SDAn) SCKn (SCLn) 0 3.45*2 00.9*3 μs Data setup time SDA ↓ ↑→ SCL↑ tSUDAT SOUTn (SDAn) SCKn (SCLn) 250 ⎯ 100 ⎯ ns “STOP condition” setup time SCL ↑→ SDA↑ tSUSTO SOUTn (SDAn) SCKn (SCLn) 4.0 ⎯ 0.6 ⎯μs Bus free time between “STOP condition” and “START condition” tBUF ⎯ 4.7 ⎯ 1.3 ⎯μs Noise filter tSP ⎯⎯ 2 tCYCP *4 ⎯ 2 tCYCP *4 ⎯ ns |
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