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PCIMX515CJM6C Datasheet(PDF) 37 Page - Freescale Semiconductor, Inc |
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PCIMX515CJM6C Datasheet(HTML) 37 Page - Freescale Semiconductor, Inc |
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37 / 184 page ![]() Electrical Characteristics i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 Freescale Semiconductor 37 Preliminary—Subject to Change Without Notice 3.6.4 Clock Amplifier Parameters (CKIH1, CKIH2) The input to Clock Amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave or sinusoidal frequency source. No external series capacitors are required 3.6.5 DPLL Electrical Parameters Table 34. CAMP Electrical Parameters (CKIH1, CKIH2) Parameter Min Typ Max Unit Input frequency 8.0 — 40.0 MHz VIL (for square wave input) 0 — 0.3 V VIH (for square wave input) (VCC 1 –0.25) 1 VCC is the supply voltage of CAMP. —3 V Sinusoidal input amplitude 0.4 2 2 This value of the sinusoidal input will be determined during characterization. —VDD Vp-p Output duty cycle 45 50 55 % Table 35. DPLL Electrical Parameters Parameter Test Conditions/Remarks Min Typ Max Unit Reference clock frequency range1 1 Device input range cannot exceed the electrical specifications of the CAMP, see Table 34. — 10 — 100 MHz Reference clock frequency range after pre-divider —10 — 40 MHz Output clock frequency range (dpdck_2) — 300 — 1025 MHz Pre-division factor2 2 The values specified here are internal to DPLL. Inside the DPLL, a “1” is added to the value specified by the user.Therefore, the user has to enter a value “1” less than the desired value at the inputs of DPLL for PDF and MFD. —1 — 16 — Multiplication factor integer part — 5 — 15 — Multiplication factor numerator3 Should be less than denominator –67108862 — 67108862 — Multiplication factor denominator2 — 1 — 67108863 — Output Duty Cycle — 48.5 50 51.5 % Frequency lock time4 (FOL mode or non-integer MF) —— — 398 Tdpdref Phase lock time — — — 100 µs Frequency jitter5 (peak value) — — 0.02 0.04 Tdck Phase jitter (peak value) FPL mode, integer and fractional MF — 2.0 3.5 ns Power dissipation fdck = 300 MHz @ avdd = 1.8 V, dvdd = 1.2 V fdck = 650 MHz @ avdd = 1.8 V, dvdd = 1.2 V — — 0.65 (avdd) 0.92 (dvdd) 1.98 (avdd) 1.8 (dvdd) mW |
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