PCIMX515CJM6C datasheet(71/184 Pages) FREESCALE

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Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

3.7.6.2

High-Speed Mode Timing Parameters

Figure 45 depicts the high-speed mode timings of HS-I2C module, and Table 63 lists the timing

characteristics.

Figure 45. High-Speed Mode Timing

Table 63. HS-I2C High-Speed Mode Timing Parameters

Parameter

High-Speed Mode

Unit

Min

Max

IC1

SCLH cycle time

3.4

MHz

IC2

Setup time (repeated) START condition

160

—

IC3

Hold time (repeated) START condition

160

—

IC4

LOW Period of the SCLH Clock

160

—

IC5

HIGH Period of SCLH Clock

—

IC6

Data set-up time

—

IC7

Data hold time

1 A device must internally provide a hold time of at least 300 ns for SDAH signal in order to bridge the undefined region of the

falling edge of SCLH.

IC8

Rise time of SCLH

IC9

Rise time of SCLH signal after a repeated START condition and after an acknowledge bit

IC10 Fall time of SCLH signal

IC11 Rise time of SDAH signal

IC12 Fall time of SDAH signal

IC13 Set-up time for STOP condition

160

—

IC14 Capacitive load for each bus line (Cb)

—

100

IC11

IC12

IC3

IC6

IC7

IC2

IC13

IC4

IC9

IC5

IC10

START

STOP

START

SDAH

SCLH

IC1

IC8

PCIMX515CJM6C Datasheet(PDF) 71 Page - Freescale Semiconductor, Inc

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