PCIMX515CJM6C datasheet(52/184 Pages) FREESCALE

52 / 184 page

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Electrical Characteristics

WE34 WE_B Invalid to CSx_B Invalid

WE7 – WE9 + (WEN – CSN)

—

3 – (WEN_CSN)

WE35 CSx_B Valid to OE_B Valid

WE10 – WE6 + (OEA – CSA)

—

3 + (OEA – CSA)

WE36 OE_B Invalid to CSx_B Invalid

WE7 – WE11 + (OEN – CSN)

—

3 – (OEN – CSN)

WE37 CSx_B Valid to BEy_B Valid

(Read access)

WE12 – WE6 + (RBEA – CSA)

—

3 + (RBEA4 – CSA)

WE38 BEy_B Invalid to CSx_B Invalid

(Read access)

WE7 – WE13 + (RBEN – CSN)

—

3 – (RBEN5 – CSN)

WE39 CSx_B Valid to ADV_B Valid

WE14 – WE6 + (ADV – CSA)

—

3 + (ADVA – CSA)

WE40 ADV_B Invalid to CSx_B Invalid

(ADVL is asserted)

WE7 – WE15 – CSN

—

3 – CSN

WE41 CSx_B Valid to Output Data

Valid

WE16 – WE6 – WCSA

—

3 – WCSA

WE42 Output Data Invalid to CSx_B

Invalid

WE17 – WE7 – CSN

—

3 – CSN

WE43 Input Data Valid to CSx_B

Invalid

MAXCO + MAXDI

MAXCO6 + MAXDI7

—ns

WE44 CSx_B Invalid to Input Data

invalid

—

WE45 CSx_B Valid to BEy_B Valid

(Write access)

WE12 – WE6 + (WBEA – CSA)

—

3 + (WBEA – CSA)

WE46 BEy_B Invalid to CSx_B Invalid

(Write access)

WE7 – WE13 + (WBEN – CSN)

—

–3 + (WBEN – CSN)

WE47 Dtack Valid to CSx_B Invalid

MAXCO + MAXDTI

MAXCO6 + MAXDTI8

—ns

WE48 CSx_B Invalid to Dtack invalid

—

1 Parameters WE4... WE21 value see in the Table 41.

2 CS Assertion. This bit field determines when CS signal is asserted during read/write cycles.

3 CS Negation. This bit field determines when CS signal is negated during read/write cycles.

4 BE Assertion. This bit field determines when BE signal is asserted during read cycles.

5 BE Negation. This bit field determines when BE signal is negated during read cycles.

6 Output maximum delay from internal driving the FFs to chip outputs. The Max. delay between all memory controls (addr,

csx_b, oe_b, we_b, bey_b, and adv_b)

7 Maximum delay from chip input data to internal FFs. The max. delay between all data input pins.

8 DTACK maximum delay from chip input data to internal FF.

Table 41. WEIM Asynchronous Timing Parameters Table Relative Chip Select (continued)

Parameter

Determination by

Synchronous Measured

Parameters 1

Min

Max

Unit

PCIMX515CJM6C Datasheet(PDF) 52 Page - Freescale Semiconductor, Inc

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