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PCIMX515CJM6C Datasheet(PDF) 38 Page - Freescale Semiconductor, Inc

Part # PCIMX515CJM6C
Description  i.MX51 Applications Processors for Consumer and Industrial Products
PDF  184 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PCIMX515CJM6C Datasheet(HTML) 38 Page - Freescale Semiconductor, Inc

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i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1
38
Freescale Semiconductor
Preliminary—Subject to Change Without Notice
Electrical Characteristics
3.6.6
NAND Flash Controller (NFC) Parameters
This section provides the relative timing requirements among different signals of NFC at the module level
in the different operational modes.
Timing parameters in Figure 12, through Figure 15, Figure 17, and Table 37 show the default NFC mode
(asymmetric mode) using two Flash clock cycles per one access of RE_B and WE_B.
Timing parameters in Figure 12, Figure 13, Figure 14, Figure 16, Figure 17, and Table 37 show symmetric
NFC mode using one Flash clock cycle per one access of RE_B and WE_B.
With reference to the timing diagrams, a high is defined as 80% of signal value and low is defined as 20%
of signal value. All parameters are given in nanoseconds. The BGA contact load used in calculations is 20
pF (except for NF16 - 40 pF) and there is max drive strength on all contacts.
All timing parameters are a function of T, which is the period of the flash_clk clock (“enfc_clk” at system
level). This clock frequency can be controlled by the user, configuring CCM (SoC clock controller). The
clock is derived from emi_slow_clk after single divider. Table 36 demonstrates few examples for clock
frequency settings.
3 The maximum total multiplication factor (MFI + MFN/MFD) allowed is 15.Therefore, if the MFI value is 15, MFN value must be
zero.
4 T
dpdref is the time period of the reference clock after predivider.According to the specification, the maximum lock time in FOL
mode is 398 cycles of divided reference clock when DPLL starts after full reset.
5 Tdck is the time period of the output clock, dpdck_2.
Table 36. NFC Clock Settings Examples
emi_slow_clk (MHz)
nfc_podf (Division Factor)
enfc_clk (MHz)
T—Clock Period (ns)1
1 Rounded up to whole nanoseconds.
133 (max value)
5 (reset value)
26.6
38
133
4
33.25
31
133
3
44.33
23



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