PCIMX515CJM6C datasheet(19/184 Pages) FREESCALE

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Electrical Characteristics

i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Table 11 shows the current core consumption (not including I/O) of the i.MX51.

Table 11. i.MX51 Stop Mode Current and Power Consumption 1

Mode

Condition

Supply

Nominal

Unit

Stop Mode

• External reference clocks

gated

• Power gating for ARM and

processing units

• Stop mode voltage

VDDGP = 0.85 V, VCC = 0.95 V, VDDA = 0.95 V

ARM CORE in SRPG mode

L1 and L2 caches power gated

IPU in S&RPG mode

VPU and GPU in PG mode

All PLLs off, all CCM-generated clocks off

CKIL input on with 32 kHz signal present

All modules disabled

USBPHY PLL off

External (MHz) crystal and on-chip oscillator

powered down (SBYOS bit asserted)

No external resistive loads that cause current flow

Standby voltage allowed (VSTBY bit is asserted)

TA = 25

°C

VDDGP

0.18

VCC

0.35

VDDA

0.15

NVCC_OSC

0.012

Total

0.66

Stop Mode

• External reference clocks

gated

• Power gating for ARM and

processing units

• HPM voltage

VDDGP = 1.1 V, VCC = 1.225 V, VDDA = 1.2 V

ARM CORE in SRPG mode

L1 and L2 caches power gated

IPU in S&RPG mode

VPU and GPU in PG mode

All PLLs off, all CCM-generated clocks off

CKIL input on with 32 kHz signal present

All modules disabled.

USBPHY PLL off

External (MHz) crystal and on-chip oscillator

powered down (SBYOS bit asserted)

No external resistive loads that cause current flow

TA = 25

°C

VDDGP

0.24

VCC

0.45

VDDA

0.2

NVCC_OSC

0.012

Total

1.09

Stop Mode

• External reference clocks

enabled

• Power gating for ARM and

processing units

• HPM voltage

VDDGP = 1.1 V, VCC = 1.225 V, VDDA = 1.20 V

ARM CORE in SRPG mode

L1 and L2 caches power gated

IPU in S&RPG mode

VPU and GPU in PG mode

All PLLs off, all CCM-generated clocks off

CKIL input on with 32 kHz signal present

All modules disabled

USBPHY PLL off

External (MHz) crystal and on-chip oscillator pow-

ered and generating reference clock

No external resistive loads that cause current flow

TA = 25

°C

VDDGP

0.24

VCC

0.45

VDDA

0.2

NVCC_OSC

1.5

Total

4.8

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