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PCIMX515CJM6C Datasheet(PDF) 56 Page - Freescale Semiconductor, Inc |
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PCIMX515CJM6C Datasheet(HTML) 56 Page - Freescale Semiconductor, Inc |
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56 / 184 page  i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1 56 Freescale Semiconductor Preliminary—Subject to Change Without Notice Electrical Characteristics 3.6.9 DDR2 SDRAM Specific Parameters Figure 32 shows the timing parameters for DDR2. The timing parameters for this diagram appear in Table 45. Figure 32. DDR2 SDRAM Basic Timing Parameters Table 45. DDR2 SDRAM Timing Parameter Table ID Parameter Symbol SDCLK = 200 MHz Unit Min Max DDR1 SDRAM clock high-level width tCH 0.45 0.55 tCK DDR2 SDRAM clock low-level width tCL 0.45 0.55 tCK DDR3 SDRAM clock cycle time tCK 5— ns DDR4 CS, RAS, CAS, CKE, WE, ODT setup time tIS1 0.35 — ns DDR5 CS, RAS, CAS, CKE, WE, ODT hold time tIH1 0.475 — ns SDCLK WE ADDR ROW/BA COL/BA CS CAS RAS DDR1 DDR3 DDR2 DDR4 DDR4 DDR4 DDR5 DDR5 DDR5 DDR5 DDR6 DDR7 SDCLK ODT/CKE DDR4 |
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