AT90SCR100 datasheet(187/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

Figure 15-11.

SCIB Interrupt Sources

This signal is high level active. Each of the sources is able to activate the SCIB interruption

which is cleared by software by clearing the corresponding bits in the Smart Card Interrupt

If another interrupt occurs during the read of the Smart Card Interrupt register, the activation of

the corresponding bit in the Smart Card Interrupt register and the new SCIB interruption is

delayed until the interrupt register is read by the microcontroller.

15.6

Additional Features

15.6.1

Clock

The clkSCI input must be in the range 1 - 5 MHz according to ISO 7816.

The clkSCI can be programmed up to 12 MHz. In this case, the timing specification of the output

buffer will not be ISO 7816 compliant.

Please refer to section “Clock System” on page 31 for the description of the input clock.

The dividers values are designed to access most common frequencies of ISO7816 norm. See

section “SCICLK - Smart Card Clock Register” on page 199, for the clock frequency available in

output of the Smart Card interface.

15.6.2

Card Presence Input

The CPRES input can generate an interrupt. To do so, global interrupt must be enabled and

SCIER.CARDINE must be set. The CPRES interrupt is generated by an event on CPRES (i.e. a

high or low edge depending on the setting of SCICR.CARDDET).

Each bit of the SCIIR register is irrelevant while the corresponding interruption is

disabled in SCIER register. When the interruption mode is not used, the bits of the

SCISR register must be used instead of the bits of the SCIIR register.

ESCTI

SCTI

Transmission

complete

ESCRI

SCRI

SCIB

Interrupt

Reception

complete

ESCPI

SCPI

Parity error

detected

ESCWTI

SCWTI

Timer on

WT counter

EVCARDER

VCARDERR

Output voltage

out of range

ESCTBI

SCTBI

Transmit buffer

copied to shift register

Caution

AT90SCR100 Datasheet(PDF) 187 Page - ATMEL Corporation

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