H5GQ1H24AFR-R0C datasheet(98/173 Pages) HYNIX

98 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

Figure 66. DBI Flow Diagram

DBI# Pin Special Function Overview

The DBI# pin has special behavior compared to DQ pins because of the ability to enable and disable it via

MRS. For either WRITE or READ DBI# pin training, both DBI READ and DBI WRITE in MRS must be

enabled. The behavior of the DBI# pin in various mode register settings is summarized below:

If both DBI READ and DBI WRITE are enabled:

•Pin drives DBI FIFO data with RDTR command

•DBI# pin FIFO accepts WRTR data with the WRTR command

If only DBI READ is enabled:

•DBI# pin drives ODT when not READ or RDTR

If only DBI WRITE is enabled:

•Pin always drives ODT (unless RESET)

If both DBI READ and DBI WRITE are disabled:

•DBI# pin drives ODT (unless RESET)

Yes

Logical

output data

’0’ count

> 4 ?

DBI# = ’L’

Invert

data byte

DBI# = ’H’

Don’t invert

data byte

Determine ’0’ count

in data byte

Logical

input data

DBI# = ’H’

Don’t invert

data byte

DBI# = ’L’

Invert

data byte

Transmitter

Receiver

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