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H5GQ1H24AFR-R0C Datasheet(PDF) 60 Page - Hynix Semiconductor

Part # H5GQ1H24AFR-R0C
Description  1Gb (32Mx32) GDDR5 SGRAM
PDF  173 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5GQ1H24AFR-R0C Datasheet(HTML) 60 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009
60
H5GQ1H24AFR
 4.8. MODE REGISTER 7 (MR7)
Mode  Register  7  controls  features  like  PLL  Standby,  PLL  Fast‐Lock,  PLL  Delay  Compensation,  Low
Frequency  mode,  Auto  Synchronization,  Data  Preamble,  Temperature  Sensor  operation,  Half  VREFD,
VDD Range and DCC as shown in Figure 32.
The register is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=1, BA2=1
and BA3=0.
Figure 32. Mode Register 7 (MR7) Definition
Low Frequency Mode
When  Low  Frequency Mode  is  enabled by  bit A3, the  power  consumption  of  input  receivers  and clock
trees is reduced. The maximum operating frequency for this low frequency mode is given in the vendor‘s
datasheet. 
WCK2CK Auto Synchronization
GDDR5  SGRAMs  support  a  WCK2CK  automatic  synchronization  mode  that  eliminates  the  need  for
WCK2CK training upon power‐down exit or for reducing WCK2CK training time at low frequency. This
mode is controlled by bit A4. For a detailed description see WCK2CK Auto Synchronization in the section
entitled WCK2CK Training.
A11
A10
DCC
00
no DCC /
DCC off or hold / opt.
01
DCC start 
10
DCC reset l
11
RFU
A3
Low Frequency Mode
0Off
1On
A4
WCK2CK Auto Sync
0Off
1On
A5
Data Preamble
0Off
1On
A6
Temperature Sensor
0Off
1On
A7
Half VFRED
00.7 * VDDQ
10.5 * VDDQ
BA3 BA2 BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
01
11
0
DCC
RFU
Half 
VREFD
Temp 
Sense
DQ 
PreA
Auto 
Sync
LF 
Mode
RFU



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