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H5GQ1H24AFR-R0C Datasheet(PDF) 18 Page - Hynix Semiconductor

Part # H5GQ1H24AFR-R0C
Description  1Gb (32Mx32) GDDR5 SGRAM
PDF  173 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5GQ1H24AFR-R0C Datasheet(HTML) 18 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009
18
H5GQ1H24AFR
 2.3. BANK GROUPS
For GDDR5 SGRAM devices operating at frequencies above a certain threshold, the activity within a bank 
group must be restricted to ensure proper operation of the device. The 8 or 16 banks in GDDR5 SGRAMs 
are divided into four bank groups. The bank groups feature is controlled by bits A10 and A11 in Mode 
Register 3 (MR3). The assignment of the banks to the bank groups is shown in Table 7.
These bank groups allow the specification of different command delay parameters depending on whether 
back‐to‐back accesses are to banks within one bank group or across bank groups as shown in Table 8.
 
Table 7  Bank Groups
Bank
Addressing
1G
BA3
BA2
BA1
BA0
16 banks
00
000
Group A
10
001
20
010
30
011
40
100
Group B
50
101
60
110
70
111
81
000
Group C
91
001
10
1
010
11
1
011
12
1
100
Group D
13
1
101
14
1
110
15
1
111



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