H5GQ1H24AFR-R0C datasheet(54/173 Pages) HYNIX

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H5GQ1H24AFR-R0C Datasheet(PDF) 54 Page - Hynix Semiconductor

Part #	H5GQ1H24AFR-R0C

Description	1Gb (32Mx32) GDDR5 SGRAM

PDF	173 Pages

Scroll/Zoom	100%

Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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54 / 173 page

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

Read CRC

Bit A9 controls the CRC calculation for READ bursts. When enabled, the calculated CRC pattern will be

transmitted on the EDC pins with the latency as programmed in the CRCRL field of this register. With

Read CRC being off, no CRC will be calculated for READ bursts, and the EDC hold pattern will be

transmitted instead.

Write CRC

Bit A10 controls the CRC calculation for WRITE bursts. When enabled, the calculated CRC pattern will be

transmitted on the EDC pins with the latency as programmed in the CRCWL field of this register. With

Write CRC being off, no CRC will be calculated for WRITE bursts, and the EDC hold pattern will be trans‐

mitted instead.

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