H5GQ1H24AFR-R0C datasheet(14/173 Pages) HYNIX

14 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

Figure 5: Vendor ID Timing Diagram

Table 3 Revision ID & Density & FIFO Depth

Revision ID

Density

FIFO

Bit 7

Bit 6

Bit 4

Bit 9

Bit 8

Bit 11

Bit 10

00010

110

Table 4 Vendor ID to DQ mapping

Bit

MF=0

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

MF=1

DQ31

DQ30

DQ29

DQ28

DQ27

DQ26

DQ25

DQ24

Feature

Revision Identification

Manufacturers Vendor Code

Bit

MF=0

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

MF=1

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

Feature

RFU

FIFO Depth

Density

CK#

CMD

BA0‐BA3

A2‐A5

A9,A10

A0,A1

A11

MRA

Code

tWRIDON(max)

tWRIDOFF(min)

Vendor ID + Rev Code

MRA = Mode Register Address; Code = Opcode to be loaded

NOP

MRS

NOP

MRS

NOP

Donʹt Care

Code

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