H5GQ1H24AFR-R0C datasheet(17/173 Pages) HYNIX

Part #	H5GQ1H24AFR-R0C

Description	1Gb (32Mx32) GDDR5 SGRAM

PDF	173 Pages

Scroll/Zoom	100%

Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

Logo

17 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

The flow diagram in Figure 7 illustrates the ABI operation. The controller decides whether to invert or not

invert the data conveyed on the address lines. The GDDR5 SGRAM has to perform the reverse operation

based on the level of the ABI# pin. Address input timing parameters are only valid with ABI being enabled

and a maximum of 4 address inputs driven Low.

Figure 7: Address Bus Inversion (ABI) Flow Diagram

Data to be sent

on address lines

’0’ count

> 4 ?

ABI# = ’L’

Invert

Yes

ABI# = ’H’

Don’t invert

Determine ’0’

count

Data received

on address lines

ABI# = ’H’

Don’t invert

ABI# = ’L’

Invert

Controller

GDDR5

SGRAM

H5GQ1H24AFR-R0C Datasheet(PDF) 17 Page - Hynix Semiconductor