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H5GQ1H24AFR-R0C Datasheet(PDF) 55 Page - Hynix Semiconductor |
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H5GQ1H24AFR-R0C Datasheet(HTML) 55 Page - Hynix Semiconductor |
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55 / 173 page  This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsability for use of circuits described. No patent licenses are implied. Rev. 1.0 /Nov. 2009 55 H5GQ1H24AFR 4.6. MODE REGISTER 5 (MR5) Mode Register 5 defines digital RAS, PLL band‐width and low power modes as shown in Figure 29. The register is programmed via the MODE REGISTER SET (MRS) command with BA0=1, BA1=0, BA2=1 and BA3=0. Figure 29. Mode Register 5 (MR5) Definition A1 LP2 0Off 1On BA3 BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 01 010 RFU PLL Bandwidth LP3 LP2 RFU A5 A4 A3 ‐3dB [MHz] BW3dBLL Peak [MHz] BWPKLL Peak [dB] PKLL 00 0 13 2 ＜1.2 00 1 18 4 ＜1.1 01 0 22 5 ＜1.1 01 1 28 7 ＜1.2 10 0 36 10 ＜1.2 10 1 44 13 ＜1.2 11 0 54 15 ＜1.7 11 1 69 20 ＜1.5 A2 LP3 0Off 1On Note 1) PLL BW characteristics is extracted at 4Gbps Note 2) PLL BW is linearly proportional to the data rate |
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