Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

H5GQ1H24AFR-R0C Datasheet(PDF) 57 Page - Hynix Semiconductor

Part # H5GQ1H24AFR-R0C
Description  1Gb (32Mx32) GDDR5 SGRAM
PDF  173 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

H5GQ1H24AFR-R0C Datasheet(HTML) 57 Page - Hynix Semiconductor

Back Button H5GQ1H24AFR-R0C Datasheet HTML 53Page - Hynix Semiconductor H5GQ1H24AFR-R0C Datasheet HTML 54Page - Hynix Semiconductor H5GQ1H24AFR-R0C Datasheet HTML 55Page - Hynix Semiconductor H5GQ1H24AFR-R0C Datasheet HTML 56Page - Hynix Semiconductor H5GQ1H24AFR-R0C Datasheet HTML 57Page - Hynix Semiconductor H5GQ1H24AFR-R0C Datasheet HTML 58Page - Hynix Semiconductor H5GQ1H24AFR-R0C Datasheet HTML 59Page - Hynix Semiconductor H5GQ1H24AFR-R0C Datasheet HTML 60Page - Hynix Semiconductor H5GQ1H24AFR-R0C Datasheet HTML 61Page - Hynix Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 57 / 173 page
background image
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009
57
H5GQ1H24AFR
 4.7. MODE REGISTER 6 (MR6)
Mode  Register  6  controls  the  WCK2CK  alignment  point  and  defines  VREFD  related  features  such  as
source, level, offsets, VREFD Merge and VREFD Auto Calibration mode, as shown in Figure 30.
The register is programmed via the MODE REGISTER SET (MRS) command with BA0=0, BA1=1, BA2=1
and BA3=0.
Figure 30. Mode Register 6 (MR6) Definition
WCK2CK Alignment Point (WCKPIN)
Bit A0 defines the position of the alignment point between CK and WCK. When set to ‘0‘, the alignment
point will be at the phase detector inside the GDDR5 SGRAM. When set to ‘1‘, the alignment point will be
at the CK and WCK pins. 
Input Reference Voltage for DQ and DBI# Pins
GDDR5 SGRAMs offer multiple options for the input reference voltage (Vref) for the DQ and DBI# pins,
as shown in Figure 31. 
A11
A10
A9
A8
VREFD 
Offset
00
00
0 / 
default
00
01
+1
00
10
+2
00
11
+3
01
00
+4
01
01
+5
01
10
+6
01
11
+7
10
00
0 / Auto 
(opt.)
10
01
‐7
10
10
‐6
10
11
‐5
11
00
‐4
11
01
‐3
11
10
‐2
11
11
‐1
BA3 BA2 BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
01
10
0
VREFD Offset
Bytes in rows A‐F
VREFD Offset
Bytes in rows M‐U
VREFD Auto
VREFD
VREFD 
Merge
WCK 
PIN
A3
VREFD
0external VREFD pins
1
internally generated
A1
VREFD Merge
0Off
1On
A7
A6
A5
A4
VREFD 
Offset
000
0
0 / 
default
000
1
+1
001
0
+2
001
1
+3
010
0
+4
010
1
+5
011
0
+6
011
1
+7
100
0
0 / Auto 
(opt.)
100
1
‐7
101
0
‐6
101
1
‐5
110
0
‐4
110
1
‐3
111
0
‐2
111
1
‐1
A0
WCK2CK 
Alignment Pt.
0
PD inside 
DRAM
1PD at pins



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com