H5GQ1H24AFR-R0C datasheet(103/173 Pages) HYNIX

103 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

103

H5GQ1H24AFR

5.13. PRECHARGE

The PRECHARGE command (see Figure 68) is used to deactivate the open row in a particular bank (PRE)

or the open row in all banks (PREALL). The bank(s) will be available for a subsequent row access a speci‐

fied time (tRP) after the PRECHARGE command is issued as illustrated in Figure 39.

Input A8 determines whether one or all banks are to be precharged. In case where only one bank is to be

precharged, inputs BA0‐BA3 select the bank. Otherwise BA0‐BA3 are treated as “Don’t Care”.

Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE

command being issued. A PRECHARGE command will be treated as a NOP if there is no open row in that

bank, or if the previously open row is already in the process of precharging. Sequences of PRECHARGE

commands must be spaced by at least tPPD as shown in Figure 69.

Figure 68. PRECHARGE command

Figure 69. Precharge to Precharge Timings

BA = Bank Address (if A8 is LOW;

otherwise Donʹt Care)

CS#

WE#

CAS#

RAS#

CKE#

A9‐A11(A12)

A0,A1,A6,A7

BA0‐BA3

A2‐A5

LOW

PREALL

PRE

Precharge

CK#

CMD

NOP

BAx,y = bank address x,y

ADDR

PRE

NOP

PRE

NOP

BAy

tPPD

BAx

tRAS

tRP

Donʹt Care

H5GQ1H24AFR-R0C Datasheet(PDF) 103 Page - Hynix Semiconductor

H5GQ1H24AFR-R0C Datasheet(HTML) 103 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL