H5GQ1H24AFR-R0C datasheet(129/173 Pages) HYNIX

129 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

129

H5GQ1H24AFR

NOTE: Min

tRC or tRFC for IDD measurements is the smallest multiple of tCK that meets the minimum of the absolute value for the

respective parameter.

Common Test conditions:

Device is configured to x32 mode

ABI and DBI are enabled

All ODTs are enabled with ZQ/2

4) PLLs are enabled unless otherwise noted

CRC is enabled for READs and WRITEs, and the EDC hold pattern is programmed to’1010’

Bank groups are enabled if required for device operation at tCK(min)

Address inputs include ABI# pin

Each data byte consists of eight DQs and one DBI# pin

DESELECT condition during idle command cycles

Table 42 IDD Specifications and Test Conditions

PARAMETER/CONDITION

SYMBOL

NOTES

One Bank Activate Precharge Current: tCK = tCK(min); tWCK = tWCK(min); tRC = tRC(min); CKE# =

LOW; DQ, DBI# are HIGH; random bank and row addresses (4 address inputs set LOW) with ACT

command

IDD0

One Bank Activate Read Precharge Current: tCK = tCK (min); tWCK = tWCK(min);

tRC = tRC(min); CKE# = LOW; one bank activated; single read burst with 50% data toggle on each data

transfer, with 4 outputs per data byte driven LOW; otherwise DQ, DBI# are HIGH; random bank, row

and column addresses (4 address inputs set LOW) with ACT and READ commands; IOUT = 0mA

IDD1

Precharge Power‐down Current: tCK = tCK (min); tWCK = tWCK(min); all banks idle;

CKE# = HIGH; all other inputs are HIGH; PLLs are off

IDD2P

Precharge Standby Current: tCK = tCK (min); tWCK = tWCK(min); all banks idle;

CKE# = LOW; all other inputs are HIGH

IDD2N

Active Power‐down Current: tCK = tCK (min); tWCK = tWCK(min); one bank active;

CKE# = HIGH; all other inputs are HIGH

IDD3P

Active Standby Current: tCK = tCK (min); tWCK = tWCK(min); one bank active;

CKE# = LOW; all other inputs are HIGH

IDD3N

Read Burst Current: tCK = tCK (min); tWCK = tWCK(min); CKE# = LOW; one bank in each of the 4 bank

groups activated; continuous read burst across bank groups with 50% data toggle on each data

transfer, with 4 outputs per data byte driven LOW; random bank and column addresses (4 address

inputs set LOW) with READ command; IOUT = 0mA

IDD4R

Write Burst Current: tCK = tCK (min); tWCK = tWCK(min); CKE# = LOW; one bank in each of the 4 bank

groups activated; continuous write burst across bank groups with 50% data toggle on each data

transfer, with 4 inputs per data byte set LOW; random bank and column addresses (4 address inputs

set LOW) with WRITE command; no data mask

IDD4W

Refresh Current: tCK = tCK (min); tWCK = tWCK(min); tRFC = tRFC(min); CKE# = LOW;

DQ, DBI# are HIGH; address inputs are HIGH

IDD5

Self Refresh Current: CKE# = HIGH; all other inputs are HIGH

IDD6

Four Bank Interleave Read Current: tCK = tCK(min); tWCK = tWCK(min); CKE# = LOW;

one bank in each of the 4 bank groups activated and precharged at tRC(min); continuous read burst

across bank groups with 50% data toggle on each data transfer, with 4 outputs per data byte driven

LOW; random bank, row and column addresses (4 address inputs set LOW) with ACT and READ/

READA commands; IOUT = 0mA

IDD7

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