PIC16F1933-ESLASHP datasheet(191/418 Pages) MICROCHIP

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Preliminary

DS41364A-page 189

PIC16F193X/LF193X

19.4

Compare Mode

In Compare mode, the 16-bit CCPRx register value is

constantly compared against the TMR1 register pair

value. When a match occurs, the CCPx module may:

• Toggle the CCPx output

• Set the CCPx output

• Clear the CCPx output

• Generate a Special Event Trigger

• Generate a Software Interrupt

The action on the pin is based on the value of the

CCPxM<3:0> control bits of the CCPxCON register. At

the same time, the interrupt flag CCPxIF bit is set.

All Compare modes can generate an interrupt.

FIGURE 19-2:

COMPARE MODE

OPERATION BLOCK

DIAGRAM

19.4.1

CCPX PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the associated TRIS bit.

Also, the CCPx pin function can be moved to

alternative pins using the APFCON register. Refer to

Section 6.1 “Alternate Pin Function” for more

details.

19.4.2

TIMER1 MODE SELECTION

In Compare mode, Timer1 must be running in either

Timer mode or Synchronized Counter mode. The

compare operation may not work in Asynchronous

Counter mode.

19.4.3

SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen

(CCPxM<3:0> = 1010), the CCPx module does not

assert control of the CCPx pin (see the CCP1CON

19.4.4

SPECIAL EVENT TRIGGER

When

Special

Event

Trigger

mode

chosen

(CCPxM<3:0> = 1011), the CCPx module does the

following:

• Resets Timer1

• Starts an ADC conversion if ADC is enabled

(CCP5 only)

The CCPx module does not assert control of the CCPx

pin in this mode (see the CCPxCON register).

The Special Event Trigger output of the CCP occurs

immediately upon a match between the TMR1H,

TMR1L register pair and the CCPRxH, CCPRxL

reset until the next rising edge of the Timer1 clock. The

Special Event Trigger output starts an A/D conversion

(if the A/D module is enabled). This feature is only

available on CCP5). This allows the CCPRxH,

CCPRxL register pair to effectively provide a 16-bit

programmable period register for Timer1.

19.4.5

COMPARE DURING SLEEP

The Compare mode is dependent upon the system

clock (FOSC) for proper operation. Since FOSC is shut

down during Sleep mode, the Compare mode will not

function properly during Sleep.

Note:

Clearing the CCPxCON register will force

the CCPx compare output latch to the

default low level. This is not the PORT I/O

data latch.

CCPRxH CCPRxL

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set CCPxIF Interrupt Flag

(PIRx)

Match

TRIS

CCPxCON<3:0>

Mode Select

Output Enable

Special Event Trigger will:

•

CCP<4:1>: Reset Timer1, but not set interrupt flag bit

TMR1IF.

•

CCP5: Reset Timer1, but not set interrupt flag bit and set bit

GO/DONE (ADCON0<1>).

CCPx

Note:

Clocking Timer1 from the system clock

(FOSC) should not be used in Capture

mode. In order for Capture mode to

recognize the trigger event on the CCPx

pin, TImer1 must be clocked from the

instruction clock (FOSC/4) or from an

external clock source.

Note 1: The Special Event Trigger from the CCP

module does not set interrupt flag bit

TMR1IF of the PIR1 register.

2: Removing

the

match

condition

changing the contents of the CCPRxH

and CCPRxL register pair, between the

clock edge that generates the Special

Event Trigger and the clock edge that

generates the Timer1 Reset, will preclude

the Reset from occurring.

PIC16F1933-E/P Datasheet(PDF) 191 Page - Microchip Technology

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