SPMCK16Z4MPV20 datasheet(204/500 Pages) FREESCALE

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ANALOG-TO-DIGITAL CONVERTER

M68HC16 Z SERIES

8-18

USER’S MANUAL

NOTE

This star-point scheme still requires adequate grounding for digital

and analog subsystems in addition to the star-point ground.

Other suggestions for PCB layout in which the ADC is employed include the following:

• The analog ground must be low impedance to all analog ground points in the cir-

cuit.

• Bypass capacitors should be as close to the power pins as possible.

• The analog ground should be isolated from the digital ground. This can be done

by cutting a separate ground plane for the analog ground.

• Non-minimum traces should be utilized for connecting bypass capacitors and

filters to their corresponding ground/power points.

• Minimum distance for trace runs when possible.

8.8.4 Accommodating Positive/Negative Stress Conditions

Positive or negative stress refers to conditions which exceed nominally defined oper-

ating limits. Examples include applying a voltage exceeding the normal limit on an

input (for example, voltages outside of the suggested supply/reference ranges) or

causing currents into or out of the pin which exceed normal limits. ADC specific con-

siderations are voltages greater than VDDA,VRH or less than VSSA applied to an analog

input which cause excessive currents into or out of the input. Refer to APPENDIX A

ELECTRICAL CHARACTERISTICS on exact magnitudes.

Both stress conditions can potentially disrupt conversion results on neighboring inputs.

Parasitic devices, associated with CMOS processes, can cause an immediate disrup-

tive influence on neighboring pins. Common examples of parasitic devices are diodes

to substrate and bipolar devices with the base terminal tied to substrate (VSSI/VSSA

ground). Under stress conditions, current introduced on an adjacent pin can cause er-

rors on adjacent channels by developing a voltage drop across the adjacent external

channel source impedances.

Figure 8-7 shows an active parasitic bipolar when an input pin is subjected to negative

stress conditions. Positive stress conditions do not activate a similar parasitic device.

Figure 8-7 Input Pin Subjected to Negative Stress

ADC PAR STRESS CONN

RSTRESS

RADJACENT

ADJACENT

NEGATIVE

10K

VDD

PIN UNDER

PARASITIC

IOUT

IIN

STRESS

VOLTAGE

DEVICE

PINS

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