SPMCK16Z4MPV20 datasheet(208/500 Pages) FREESCALE

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ANALOG-TO-DIGITAL CONVERTER

M68HC16 Z SERIES

8-22

USER’S MANUAL

In Figure 8-10,RF and CF comprise the user's external filter circuit. CS is the internal

sample capacitor. Each channel has its own capacitor. CS is never precharged; it re-

tains the value of the last sample. VI is an internal voltage source used to precharge

the DAC capacitor array (CDAC) before each sample. The value of this supply is VDDA/

2, or 2.5 volts for 5-volt operation.

The following paragraphs provide a simplified description of the interaction between

the ADC and the user's external circuitry. This circuitry is assumed to be a simple RC

low-pass filter passing a signal from a source to the ADC input pin. The following sim-

plifying assumptions are made:

• The source impedance is included with the series resistor of the RC filter.

• The external capacitor is perfect (no leakage, no significant dielectric absorption

characteristics, etc.)

• All parasitic capacitance associated with the input pin is included in the value of

the external capacitor.

• Inductance is ignored.

• The “on” resistance of the internal switches is zero ohms and the “off” resistance

is infinite.

8.8.6.1 Settling Time for the External Circuit

The values for RF and CF in the user's external circuitry determine the length of time

required to charge CF to the source voltage level (VSRC).

At timet=0,S1in Figure 8-10 closes. S2 is open, disconnecting the internal circuitry

from the external circuitry. Assume that the initial voltage across CF is zero. As CF

charges, the voltage across it is determined by the following equation, where t is the

total charge time:

Whent=0,the voltage across CF = 0. As t approaches infinity, VCF will equal VSRC.

(This assumes no internal leakage.) With 10-bit resolution, 1/2 of a count is equal to

1/2048 full-scale value. Assuming worst case (VSRC = full scale), Table 8-10 shows

the required time for CF to charge to within 1/2 of a count of the actual source voltage

during 10-bit conversions. Table 8-10 is based on the RC network in Figure 8-10.

NOTE

The following times are completely independent of the A/D converter

architecture (assuming the ADC is not affecting the charging).

SRC 1e

–

FCF

⁄

()

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