SPMCK16Z4MPV20 datasheet(212/500 Pages) FREESCALE

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QUEUED SERIAL MODULE

M68HC16 Z SERIES

9-2

USER’S MANUAL

The SCI provides a standard non-return to zero (NRZ) mark/space format. It operates

in either full- or half-duplex mode. There are separate transmitter and receiver enable

bits and dual data buffers. A modulus-type baud rate generator provides rates from

110 baud to 781 kbaud with a 25.17 MHz system clock. Word length of either eight or

nine bits is software selectable. Optional parity generation and detection provide either

even or odd parity check capability. Advanced error detection circuitry catches glitches

of up to 1/16 of a bit time in duration. Wake-up functions allow the CPU16 to run unin-

terrupted until meaningful data is available.

9.2 QSM Registers and Address Map

There are four types of QSM registers: QSM global registers, QSM pin control regis-

ters, QSPI registers, and SCI registers. Refer to 9.2.1 QSM Global Registers and

9.2.2 QSM Pin Control Registers for a discussion of global and pin control registers.

Refer to 9.3.1 QSPI Registers and 9.4.1 SCI Registers for further information about

QSPI and SCI registers. Writes to unimplemented register bits have no effect, and

reads of unimplemented bits always return zero.

Refer to D.6 Queued Serial Module for a QSM address map and register bit and field

definitions. Refer to 5.2.1 Module Mapping for more information about how the state

of MM affects the system.

9.2.1 QSM Global Registers

The QSM configuration register (QSMCR) controls the interface between the QSM

and the intermodule bus. The QSM test register (QTEST) is used during factory test

of the QSM. The QSM interrupt level register (QILR) determines the priority of inter-

rupts requested by the QSM and the vector used when an interrupt is acknowledged.

The QSM interrupt vector register (QIVR) contains the interrupt vector for both QSM

submodules. QILR and QIVR are 8-bit registers located at the same word address.

9.2.1.1 Low-Power Stop Mode Operation

When the STOP bit in QSMCR is set, the system clock input to the QSM is disabled

and the module enters low-power stop mode. QSMCR is the only register guaranteed

to be readable while STOP is asserted. The QSPI RAM is not readable in low-power

stop mode. However, writes to RAM or any register are guaranteed valid while STOP

is asserted. STOP can be set by the CPU16 and by reset.

The QSPI and SCI must be brought to an orderly stop before asserting STOP to avoid

data corruption. To accomplish this, disable QSM interrupts or set the interrupt priority

level mask in the CPU16 condition code register to a value higher than the IRQ level

requested by the QSM. The SCI receiver and transmitter should be disabled after

transfers in progress are complete. The QSPI can be halted by setting the HALT bit in

SPCR3 and then setting STOP after the HALTA flag is set. Refer to 5.3.4 Low-Power

Operation for more information about low-power stop mode.

Freescale Semiconductor, Inc.

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