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SPMCK16Z4MPV20 Datasheet(PDF) 214 Page - Freescale Semiconductor, Inc

Part # SPMCK16Z4MPV20
Description  M68HC16Z Series
PDF  500 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

SPMCK16Z4MPV20 Datasheet(HTML) 214 Page - Freescale Semiconductor, Inc

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QUEUED SERIAL MODULE
M68HC16 Z SERIES
9-4
USER’S MANUAL
9.2.2 QSM Pin Control Registers
The QSM uses nine pins. Eight of the pins can be used for serial communication or for
parallel I/O. Clearing a bit in the port QS pin assignment register (PQSPAR) assigns
the corresponding pin to general-purpose I/O; setting a bit assigns the pin to the QSPI.
PQSPAR does not affect operation of the SCI.
The port QS data direction register (DDRQS) determines whether pins are inputs or
outputs. Clearing a bit makes the corresponding pin an input; setting a bit makes the
pin an output. DDRQS affects both QSPI function and I/O function. DDQS7 deter-
mines the direction of the TXD pin only when the SCI transmitter is disabled. When the
SCI transmitter is enabled, the TXD pin is an output.
The port QS data register (PORTQS) latches I/O data. PORTQS writes drive pins de-
fined as outputs. PORTQS reads return data present on the pins. To avoid driving un-
defined data, first write PORTQS, then configure DDRQS.
PQSPAR and DDRQS are 8-bit registers located at the same word address. Refer to
Table 9-1 for a summary of QSM pin functions.
Table 9-1 Effect of DDRQS on QSM Pin Function
QSM Pin
QSPI Mode
DDRQS Bit
Bit State
Pin Function
MISO
Master
DDQS0
0
Serial data input to QSPI
1
Disables data input
Slave
0
Disables data output
1
Serial data output from QSPI
MOSI
Master
DDQS1
0
Disables data output
1
Serial data output from QSPI
Slave
0
Serial data input to QSPI
1
Disables data input
SCK1
NOTES:
1. PQS2 is a digital I/O pin unless the SPI is enabled (SPE set in SPCR1), in which case it
becomes the QSPI serial clock SCK.
Master
DDQS2
—
Clock output from QSPI
Slave
—
Clock input to QSPI
PCS0/SS
Master
DDQS3
0
Assertion causes mode fault
1
Chip-select output
Slave
0
QSPI slave select input
1
Disables slave select input
PCS[1:3]
Master
DDQS[4:6]
0
Disables chip-select output
1
Chip-select output
Slave
0
Inactive
1
Inactive
TXD2
2. PQS7 is a digital I/O pin unless the SCI transmitter is enabled (TE set in SCCR1), in
which case it becomes the SCI serial data output TXD.
—
DDQS7
X
Serial data output from SCI
RXD
—
None
NA
Serial data input to SCI
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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