SPMCK16Z4MPV20 datasheet(216/500 Pages) FREESCALE

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QUEUED SERIAL MODULE

M68HC16 Z SERIES

9-6

USER’S MANUAL

The serial transfer length is programmable from eight to sixteen bits, inclusive. An in-

ter-transfer delay of 17 to 8192 system clocks can be specified (default is 17 system

clocks).

A dedicated 80-byte RAM is used to store received data, data to be transmitted, and

a queue of commands. The CPU16 can access these locations directly.

The command queue allows the QSPI to perform up to 16 serial transfers without

CPU16 intervention. Each queue entry contains all the information needed by the

QSPI to independently complete one serial transfer.

A pointer identifies the queue location containing the data and command for the next

serial transfer. Normally, the pointer address is incremented after each serial transfer,

but the CPU16 can change the pointer value at any time. Support for multiple-tasks

can be provided by segmenting the queue.

The QSPI has four peripheral chip-select pins. The chip-select signals simplify inter-

facing by reducing CPU16 intervention. If the chip-select signals are externally decod-

ed, 16 independent select signals can be generated.

Wrap-around mode allows continuous execution of queued commands. In wrap-

around mode, newly received data replaces previously received data in the receive

RAM. Wrap-around mode can simplify the interface with A/D converters by continu-

ously updating conversion values stored in the RAM.

Continuous transfer mode allows an uninterrupted bit stream of eight to 256 bits in

length to be transferred without CPU16 intervention. Longer transfers are possible, but

minimal intervention is required to prevent loss of data. A standard delay of 17 system

clocks is inserted between the transfer of each queue entry.

9.3.1 QSPI Registers

The programmer’s model for the QSPI consists of the QSM global and pin control reg-

isters, four QSPI control registers (SPCR[0:3]), the status register (SPSR), and the 80-

byte QSPI RAM. Registers and RAM can be read and written by the CPU16. Refer to

D.6 Queued Serial Module for register bit and field definitions.

9.3.1.1 Control Registers

Control registers contain parameters for configuring the QSPI and enabling various

modes of operation. The CPU16 has read and write access to all control registers. The

QSM has read access only to all bits except the SPE bit in SPCR1. Control registers

must be initialized before the QSPI is enabled to ensure proper operation. SPCR1

must be written last because it contains the QSPI enable bit (SPE).

Writing a new value to any control register except SPCR2 while the QSPI is enabled

disrupts operation. SPCR2 is buffered. New SPCR2 values become effective after

completion of the current serial transfer. Rewriting NEWQP in SPCR2 causes execu-

tion to restart at the designated location. Reads of SPCR2 return the current value of

the register, not of the buffer. Writing the same value into any control register except

SPCR2 while the QSPI is enabled has no effect on QSPI operation.

Freescale Semiconductor, Inc.

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