SPMCK16Z4MPV20 datasheet(236/500 Pages) FREESCALE

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QUEUED SERIAL MODULE

M68HC16 Z SERIES

9-26

USER’S MANUAL

9.4.3.3 Baud Clock

The SCI baud rate is programmed by writing a 13-bit value to the SCBR field in SCI

control register 0 (SCCR0). The baud rate is derived from the MCU system clock by a

modulus counter. Writing a value of zero to SCBR[12:0] disables the baud rate gener-

ator. Baud rate is calculated as follows:

where SCBR[12:0] is in the range {1, 2, 3, ..., 8191}.

The SCI receiver operates asynchronously. An internal clock is necessary to synchro-

nize with an incoming data stream. The SCI baud rate generator produces a receive

time sampling clock with a frequency 16 times that of the SCI baud rate. The SCI de-

termines the position of bit boundaries from transitions within the received waveform,

and adjusts sampling points to the proper positions within the bit period.

9.4.3.4 Parity Checking

The PT bit in SCCR1 selects either even (PT = 0) or odd (PT = 1) parity. PT affects

received and transmitted data. The PE bit in SCCR1 determines whether parity check-

ing is enabled (PE = 1) or disabled (PE = 0). When PE is set, the MSB of data in a

frame is used for the parity function. For transmitted data, a parity bit is generated; for

received data, the parity bit is checked. When parity checking is enabled, the PF bit in

the SCI status register (SCSR) is set if a parity error is detected.

Enabling parity affects the number of data bits in a frame, which can in turn affect

frame size. Table 9-5 shows possible data and parity formats.

Table 9-4 Serial Frame Formats

10-Bit Frames

Start

Data

Parity/Control

Stop

—

1711

—

11-Bit Frames

Start

Data

Parity/Control

Stop

1712

1811

SCI Baud Rate

sys

SCBR[12:0]

--------------------------------------------

SCBR[12:0]

sys

SCI Baud Rate Desired

---------------------------------------------------------------------------

Freescale Semiconductor, Inc.

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