SPMCK16Z4MPV20 datasheet(237/500 Pages) FREESCALE

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M68HC16 Z SERIES

QUEUED SERIAL MODULE

USER’S MANUAL

9-27

9.4.3.5 Transmitter Operation

The transmitter consists of a serial shifter and a parallel data register (TDR) located in

the SCI data register (SCDR). The serial shifter cannot be directly accessed by the

CPU16. The transmitter is double-buffered, which means that data can be loaded into

TDR while other data is shifted out. The TE bit in SCCR1 enables (TE = 1) and dis-

ables (TE = 0) the transmitter.

The shifter output is connected to the TXD pin while the transmitter is operating (TE =

1, or TE = 0 and transmission in progress). Wired-OR operation should be specified

when more than one transmitter is used on the same SCI bus. The WOMS bit in

SCCR1 determines whether TXD is an open-drain (wired-OR) output or a normal

CMOS output. An external pull-up resistor on TXD is necessary for wired-OR opera-

tion. WOMS controls TXD function whether the pin is used by the SCI or as a general-

purpose I/O pin.

Data to be transmitted is written to SCDR, then transferred to the serial shifter. The

transmit data register empty (TDRE) flag in SCSR shows the status of TDR. When

TDRE = 0, TDR contains data that has not been transferred to the shifter. Writing to

SCDR again overwrites the data. TDRE is set when the data in TDR is transferred to

the shifter. Before new data can be written to SCDR, however, the processor must

clear TDRE by writing to SCSR. If new data is written to SCDR without first clearing

TDRE, the data will not be transmitted.

The transmission complete (TC) flag in SCSR shows transmitter shifter state. When

TC = 0, the shifter is busy. TC is set when all shifting operations are completed. TC is

not automatically cleared. The processor must clear it by first reading SCSR while TC

is set, then writing new data to SCDR.

The state of the serial shifter is checked when the TE bit is set. If TC = 1, an idle frame

is transmitted as a preamble to the following data frame. If TC = 0, the current opera-

tion continues until the final bit in the frame is sent, then the preamble is transmitted.

The TC bit is set at the end of preamble transmission.

The SBK bit in SCCR1 is used to insert break frames in a transmission. A non-zero

integer number of break frames is transmitted while SBK is set. Break transmission

begins when SBK is set, and ends with the transmission in progress at the time either

SBK or TE is cleared. If SBK is set while a transmission is in progress, that transmis-

sion finishes normally before the break begins. To assure the minimum break time,

toggle SBK quickly to one and back to zero. The TC bit is set at the end of break trans-

mission. After break transmission, at least one bit-time of logic level one (mark idle) is

transmitted to ensure that a subsequent start bit can be detected.

Table 9-5 Effect of Parity Checking on Data Size

Result

8 data bits

7 data bits, 1 parity bit

9 data bits

8 data bits, 1 parity bit

Freescale Semiconductor, Inc.

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