SPMCK16Z4MPV20 datasheet(278/500 Pages) FREESCALE

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GENERAL-PURPOSE TIMER

M68HC16 Z SERIES

11-14

USER’S MANUAL

11.8.3.1 Output Compare 1

Output compare 1 can affect any or all of OC[5:1] when an output match occurs. In

addition to allowing generation of multiple control signals from a single comparison op-

eration, this function makes it possible for two or more output compare functions to

control the state of a single OC pin. Output pulses as short as one timer count can be

generated in this way.

The OC1 action mask register (OC1M) and the OC1 action data register (OC1D) con-

trol OC1 function. Setting a bit in OC1M selects a corresponding bit in the GPT parallel

data port. Bits in OC1D determine whether selected bits are to be set or cleared when

an OC1 match occurs. Pins must be configured as outputs in order for the data in the

match occur at the same time and both attempt to alter the same pin, the OC1 function

controls the state of the pin.

11.8.3.2 Forced Output Compare

Timer compare force register (CFORC) is used to make forced compares. The action

taken as a result of a forced compare is the same as when an output compare match

occurs, except that status flags are not set. Forced channels take programmed actions

immediately after the write to CFORC.

The CFORC register is implemented as the upper byte of a 16-bit register which also

contains the PWM control register C (PWMC). It can be accessed as eight bits or a

word access can be used. Reads of force compare bits (FOC) have no meaning and

always return zeros. These bits are self-negating.

11.9 Input Capture 4/Output Compare 5

The IC4/OC5 pin can be used for input capture, output compare, or general-purpose

I/O. A function enable bit (I4/O5) in the pulse accumulator control register (PACTL)

configures the pin for input capture (IC4) or output compare function (OC5). Both bits

are cleared during reset, configuring the pin as an input, but also enabling the OC5

function. IC4/OC5 I/O functions are controlled by DDGP7 in the port GP data direction

The 16-bit register (TI4/O5) used with the IC4/OC5 function acts as an input capture

When used as the input capture 4 register, it cannot be written to except in test or

freeze mode.

11.10 Pulse Accumulator

The pulse accumulator counter (PACNT) is an 8-bit read/write up-counter. PACNT can

operate in external event counting or gated time accumulation modes. Figure 11-5 is

a block diagram of the pulse accumulator.

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SPMCK16Z4MPV20 Datasheet(PDF) 278 Page - Freescale Semiconductor, Inc