SPMCK16Z4MPV20 datasheet(279/500 Pages) FREESCALE

279 / 500 page

M68HC16 Z SERIES

GENERAL-PURPOSE TIMER

USER’S MANUAL

11-15

Figure 11-5 Pulse Accumulator Block Diagram

In event counting mode, the counter increments each time a selected transition of the

pulse accumulator input (PAI) pin is detected. The maximum clocking rate is the sys-

tem clock divided by four.

In gated time accumulation mode a clock increments PACNT while the PAI pin is in

the active state. There are four possible clock sources.

Two bits in the TFLG2 register show pulse accumulator status. The pulse accumulator

flag (PAIF) indicates that a selected edge has been detected at the PAI pin. The pulse

accumulator overflow flag (PAOVF) indicates that the pulse accumulator count has

rolled over from $FF to $00. This can be used to extend the range of the counter be-

yond eight bits.

EDGE

DETECT

LOGIC

PACNT

8-BIT COUNTER

2:1

MUX

PAI

ENABLE

OVERFLOW

INTERRUPT

REQUESTS

INTERNAL

DATA BUS

SYNCHRONIZER

DIGITAL FILTER

PACTL

TFLG2

TMSK2

MUX

PCLK

TCNT OVERFLOW

CAPTURE/COMPARE CLK

PRESCALER 512

16/32 PULSE ACC BLOCK

Freescale Semiconductor, Inc.

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SPMCK16Z4MPV20 Datasheet(PDF) 279 Page - Freescale Semiconductor, Inc

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