SPMCK16Z4MPV20 datasheet(375/500 Pages) FREESCALE

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M68HC16 Z SERIES

USER’S MANUAL

D-1

APPENDIX D

This appendix contains address maps, register diagrams, and bit/field definitions for

M68HC16 Z-series MCUs. More detailed information about register function is provid-

ed in the appropriate sections of the manual.

Except for central processing unit resources, information is presented in the intermod-

ule bus address order shown in Table D-1.

Control registers for all the modules in the microcontroller are mapped into a 4-Kbyte

block. The state of the module mapping (MM) bit in the SIM module configuration reg-

ister (SIMCR) determines where the control registers block is located in the system

memory map. When MM = 0, register addresses range from $7FF000 to $7FFFFF;

when MM = 1, register addresses range from $FFF000 to $FFFFFF.

With the CPU16, ADDR[23:20] follow the logic state of ADDR19 unless driven exter-

nally. MM corresponds to IMB ADDR23. If it is cleared, the SIM maps IMB modules

into address space $7FF000 – $7FFFFF, which is inaccessible to the CPU16. Mod-

ules remain inaccessible until reset occurs. The reset state of MM is one, but the bit is

can be written once. Initialization software should make certain it remains set.

D.1 Central Processing Unit

CPU16 registers are not part of the module address map. Figure D-1 is a functional

representation of CPU resources.

Table D-1 Module Address Map

Module

Size

(Bytes)

Base

Address

SIM

128

$YFFA00

SRAM

$YFFB00

MRM

(MC68HC16Z2/MC68HC16Z3 only)

$YFF820

ADC

$YFF700

QSM

512

$YFFC00

MCCI

(MC68HC16Z4, MC68CK16Z4 only)

$YFFC00

GPT

$YFF900

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