SPMCK16Z4MPV20 datasheet(377/500 Pages) FREESCALE

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M68HC16 Z SERIES

USER’S MANUAL

D-3

D.1.1 Condition Code Register

The CCR contains processor status flags, the interrupt priority field, and the program

counter address extension field. The CPU16 has a special set of instructions that ma-

nipulate the CCR.

S — STOP Enable

0 = Stop CPU16 clocks when LPSTOP instruction is executed.

1 = Perform NOPs when LPSTOP instruction is executed.

MV — Accumulator M overflow flag

Set when overflow into AM35 has occurred.

H — Half Carry Flag

Set when a carry from A3 or B3 occurs during BCD addition.

EV — Accumulator M Extension Overflow Flag

EV is set when an overflow into AM31 has occurred.

N — Negative Flag

N is set under the following conditions:

• When the MSB is set in the operand of a read operation.

• When the MSB is set in the result of a logic or arithmetic operation.

Z — Zero Flag

Z is set under the following conditions:

• When all bits are zero in the operand of a read operation.

• When all bits are zero in the result of a logic or arithmetic operation.

V — Overflow Flag

Set when two’s complement overflow occurs as the result of an operation.

C — Carry Flag

Set when carry or borrow occurs during arithmetic operation. Also used during shifts

and rotates.

IP[2:0] — Interrupt Priority Field

The priority value in this field (0 to 7) is used to mask low priority interrupts.

SM — Saturate Mode Bit

When SM is set, if either EV or MV is set, data read from AM using TMER or TMET is

given maximum positive or negative value, depending on the state of the AM sign bit

before overflow.

PK[3:0] — Program Counter Address Extension Field

This field is concatenated with the program counter to form a 20-bit address.

CCR — Condition Code Register

IP[2:0]

PK[3:0]

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