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SPMCK16Z4MPV20 Datasheet(PDF) 380 Page - Freescale Semiconductor, Inc |
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SPMCK16Z4MPV20 Datasheet(HTML) 380 Page - Freescale Semiconductor, Inc |
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380 / 500 page ![]() REGISTER SUMMARY M68HC16 Z SERIES D-6 USER’S MANUAL D.2.1 SIM Module Configuration Register SIMCR controls system configuration. SIMCR can be read or written at any time, ex- cept for the module mapping (MM) bit, which can only be written once after reset, and the reserved bit, which is read-only. Write has no effect. EXOFF — External Clock Off 0 = The CLKOUT pin is driven during normal operation. 1 = The CLKOUT pin is placed in a high-impedance state. FRZSW — Freeze Software Enable 0 = When FREEZE is asserted, the software watchdog and periodic interrupt timer continue to operate, allowing interrupts during background debug mode. 1 = When FREEZE is asserted, the software watchdog and periodic interrupt timer are disabled, preventing interrupts during background debug mode. FRZBM — Freeze Bus Monitor Enable 0 = When FREEZE is asserted, the bus monitor continues to operate. 1 = When FREEZE is asserted, the bus monitor is disabled. SHEN[1:0] — Show Cycle Enable The SHEN field determines how the external bus is driven during internal transfer op- erations. A show cycle allows internal transfers to be monitored externally. Table D-3 indicates whether show cycle data is driven externally, and whether exter- nal bus arbitration can occur. To prevent bus conflict, external devices must not be se- lected during show cycles. SUPV — Supervisor/User Data Space This bit has no effect because the CPU16 always operates in the supervisor mode. SIMCR — SIM Module Configuration Register $YFFA00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXOFF FRZSW FRZBM 0 RSVD1 NOTES: 1. This bit must be left at zero. Pulling DATA11 high during reset ensures this bit remains zero. A one in this bit could allow the MCU to enter an unsupported operating mode. 0 SHEN[1:0] SUPV MM 0 0 IARB[3:0] RESET: 0 1 1 0 DATA11 0 0 0 1 1 0 0 1 1 1 1 Table D-3 Show Cycle Enable Bits SHEN[1:0] Action 00 Show cycles disabled, external arbitration enabled 01 Show cycles enabled, external arbitration disabled 10 Show cycles enabled, external arbitration enabled 11 Show cycles enabled, external arbitration enabled; internal activity is halted by a bus grant Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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