SPMCK16Z4MPV20 datasheet(382/500 Pages) FREESCALE

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M68HC16 Z SERIES

D-8

USER’S MANUAL

W — Frequency Control (VCO)

This bit controls a prescaler tap in the synthesizer feedback loop. Setting this bit in-

creases the VCO speed by a factor of four. VCO relock delay is required.

X — Frequency Control (Prescaler)

This bit controls a divide by two prescaler that is not in the synthesizer feedback loop.

Setting the bit doubles clock speed without changing the VCO speed. No VCO relock

delay is required.

Y[5:0] — Frequency Control (Counter)

The Y field controls the modulus down counter in the synthesizer feedback loop, caus-

ing it to divide by a value of Y + 1. VCO relock delay is required.

EDIV — E Clock Divide Rate

0 = ECLK frequency is system clock divided by eight.

1 = ECLK frequency is system clock divided by sixteen.

SLOCK — Synthesizer Lock Flag

0 = VCO is enabled, but has not locked.

1 = VCO has locked on the desired frequency or VCO is disabled.

The MCU remains in reset until the synthesizer locks, but SLOCK does not indicate

synthesizer lock status until after the user first writes to SYNCR.

STSIM — Stop Mode SIM Clock

0 = When LPSTOP is executed, the SIM clock is driven from the external crystal

oscillator and the VCO is turned off to conserve power.

1 = When LPSTOP is executed, the SIM clock is driven from the internal VCO.

STEXT — Stop Mode External Clock

0 = When LPSTOP is executed, the CLKOUT signal is held negated to conserve

power.

1 = When LPSTOP is executed and EXOFF 1 in SIMCR, the CLKOUT signal is

driven from the SIM clock, as determined by the state of the STSIM bit.

D.2.4 Reset Status Register

RSR contains a status bit for each reset source in the MCU. RSR is updated when the

MCU comes out of reset. A set bit indicates what type of reset occurred. If multiple

sources assert reset signals at the same time, more than one bit in RSR may be set.

This register can be read at any time; a write has no effect. Bits [15:8] are unimple-

mented and always read zero.

EXT — External Reset

Reset caused by the RESET pin.

RSR — Reset Status Register

$YFFA06

NOT USED

EXT

POW

HLT

RSVD

SYS

TST

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