SPMCK16Z4MPV20 datasheet(386/500 Pages) FREESCALE

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M68HC16 Z SERIES

D-12

USER’S MANUAL

D.2.12 System Protection Control Register

This register controls system monitor functions, software watchdog clock prescaling,

and bus monitor timing. This register can be written once following power-on or reset.

Bits [15:8] are unimplemented and will always read zero.

SWE — Software Watchdog Enable

0 = Software watchdog is disabled.

1 = Software watchdog is enabled.

SWP — Software Watchdog Prescaler

This bit controls the value of the software watchdog prescaler.

0 = Software watchdog clock is not prescaled.

1 = Software watchdog clock is prescaled by 512.

The reset value of SWP is the complement of the state of the MODCLK pin during

reset.

SWT[1:0] — Software Watchdog Timing

This field selects the divide ratio used to establish the software watchdog time-out pe-

riod. Refer to Table D-6.

The following equation calculates the time-out period for a slow reference frequency,

where fref is equal to the EXTAL crystal frequency.

The following equation calculates the time-out period for a fast reference frequency,

where fref is equal to the EXTAL crystal frequency.

SYPCR — System Protection Control Register

$YFFA20

NOT USED

SWE

SWP

SWT[1:0]

HME

BME

BMT[1:0]

RESET:

MODCLK

Table D-6 Software Watchdog Divide Ratio

SWP

SWT[1:0]

Divide Ratio

000

001

211

010

213

011

215

100

218

101

220

110

222

111

224

Time-out Period

Divide Ratio Specified by SWP and SWT[1:0]

ref

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