SPMCK16Z4MPV20 datasheet(383/500 Pages) FREESCALE

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M68HC16 Z SERIES

USER’S MANUAL

D-9

POW — Power-Up Reset

Reset caused by the power-up reset circuit.

SW — Software Watchdog Reset

Reset caused by the software watchdog circuit.

HLT — Halt Monitor Reset

Reset caused by the halt monitor.

SYS — System Reset

The CPU16 does not support this function. This bit will never be set.

TST — Test Submodule Reset

Reset caused by the test submodule. Used during factory test reserved operating

mode only.

D.2.5 System Integration Test Register E

SIMTRE — System Integration Test Register E

$YFFA08

Used for factory test only.

D.2.6 Port E Data Register

This register can be accessed in two locations and can be read or written at any time.

A write to this register is stored in an internal data latch, and if any pin in the corre-

sponding port is configured as an output, the value stored for that bit is driven out on

the pin. A read of this data register returns the value at the pin only if the pin is config-

ured as a discrete input. Otherwise, the value read is the value stored in the register.

Bits [15:8] are unimplemented and will always read zero.

D.2.7 Port E Data Direction Register

Bits in this register control the direction of the port E pin drivers when pins are config-

ured for I/O. Setting a bit configures the corresponding pin as an output; clearing a bit

configures the corresponding pin as an input. This register can be read or written at

any time. Bits [15:8] are unimplemented and will always read zero.

PORTE0 — Port E0 Data Register

$YFFA10

PORTE1 — Port E1 Data Register

$YFFA12

NOT USED

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

RESET:

DDRE — Port E Data Direction Register

$YFFA14

NOT USED

DDE7

DDE6

DDE5

DDE4

DDE3

DDE2

DDE1

DDE0

RESET:

Freescale Semiconductor, Inc.

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