SPMCK16Z4MPV20 datasheet(493/500 Pages) FREESCALE

493 / 500 page

M68HC16 Z SERIES

USER’S MANUAL

I-11

registers

command RAM (CR) D-52

global registers 9-2

interrupt

level register (QILR) 9-2, D-39

vector register (QIVR) 9-2, D-39

test register (QTEST) 9-2

module configuration register (QSMCR) D-38

pin control registers 9-4

port QS

data

direction register (DDRQS) D-45

data direction register (DDRQS) 9-4

data register (PORTQS) 9-4

pin assignment register (PQSPAR)

D-45

QSPI

control register 0 (SPCR0) D-46

control register 1 (SPCR1) D-48

control register 2 (SPCR2) D-49

control register 3 (SPCR3) D-50

status register (SPSR) D-50

receive data RAM (RR) D-51

SCI

control register 0 (SCCR0) D-40

control register 1 (SCCR1) D-41

data register (SCDR) D-44

status register (SCSR) D-43

test register (QTEST) D-39

transmit data RAM (TR) D-52

types 9-2

SCI 9-21

operation 9-25

pins 9-25

registers 9-24

QSMCR D-38

QSPI 9-1, 9-5

block diagram 9-5

command RAM 9-8

enable (SPE) D-48

finished flag (SPIF) D-51

initialization operation 9-10

loop mode (LOOPQ) D-50

master operation flow 9-11

operating modes 9-9

master mode 9-9, 9-16

wraparound mode 9-19

slave mode 9-9, 9-20

wraparound mode 9-21

operation 9-8

peripheral chip-selects 9-21

pins 9-8

RAM 9-7

receive RAM 9-7

transmit RAM 9-7

registers 9-6

control registers 9-6

status register 9-7

timing A-46

— master, CPHA = 0/CPHA = 1 A-47

— slave, CPHA = 0/CPHA = 1 A-48

low voltage A-45

QTEST 9-2, D-39

Queue pointers

completed queue pointer (CPTQP) 9-8

end queue pointer (ENDQP) 9-8

new queue pointer (NEWQP) 9-8

Queued serial

module (QSM).

See QSM 9-1

peripheral interface (QSPI)

See QSPI. 9-1, 9-5

–R–

R/W 5-32

field 5-66, D-19

RAF D-43, D-63

RAM

array space (RASP) D-23

base address lock (RLCK) bit D-23

RAMBAH/BAL 6-1, D-24

RAMMCR 6-1, D-23

RAMTST 6-1, D-24

RASP 6-2, D-23

encoding 6-2, D-23

DAC array 8-5

low pass filter 8-16

RDR 9-24

RDRF 9-28, 10-21, D-43, D-63

RE 9-28, 10-4, 10-13, 10-20, D-42, D-62

Read

/write signal (R/W) 5-32

cycle 5-37

timing diagram A-29

Receive

data

(RXD) pin — QSM 9-25

(RXDA/B) pins (MCCI) 10-17

RAM 9-7

time sample clock (RT) 9-26, 9-28, 10-18, 10-21

Receiver

active (RAF) D-43, D-63

data register (RDRF) flag 9-28, 10-21

enable (RE) 9-28, 10-4, 10-13, 10-20, D-42, D-62

interrupt enable (RIE) D-42, D-61

wakeup (RWU) 9-30, 10-22, D-42, D-62

Relative addressing modes 4-10

RES10 8-7, D-31

RESET 5-48, 5-50, 5-54, 5-55

Reset

and mode select timing A-36

exception processing 5-48

module pin function out of reset 5-52

operation in SIM 5-48

control logic 5-48

mode selection 5-49

power-on 5-55

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SPMCK16Z4MPV20 Datasheet(PDF) 493 Page - Freescale Semiconductor, Inc

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