SPMCK16Z4MPV20 datasheet(104/500 Pages) FREESCALE

104 / 500 page

CENTRAL PROCESSING UNIT

M68HC16 Z SERIES

4-44

USER’S MANUAL

4.14.4.6 BDM Serial Interface

The BDM serial interface uses a synchronous protocol similar to that of the Freescale

serial peripheral interface (SPI). Figure 4-7 is a diagram of the serial logic required to

use BDM with a development system.

Figure 4-7 BDM Serial I/O Block Diagram

The development system serves as the master of the serial link, and is responsible for

the generation of the serial interface clock signal (DSCLK).

Serial clock frequency range is from DC to one-half the CPU16 clock frequency. If

DSCLK is derived from the CPU16 system clock, development system serial logic can

be synchronized with the target processor.

The serial interface operates in full-duplex mode. Data transfers occur on the falling

edge of DSCLK and are stable by the following rising edge of DSCLK. Data is trans-

mitted MSB first, and is latched on the rising edge of DSCLK.

The serial data word is 17 bits wide, which includes 16 data bits and a status/control

bit. Bit 16 indicates status of CPU-generated messages.

Command and data transfers initiated by the development system must clear bit 16.

All commands that return a result return 16 bits of data plus one status bit.

CONTROL

LOGIC

SERIAL IN

PARALLEL OUT

PARALLEL IN

SERIAL OUT

EXECUTION

UNIT

STATUS

SYNCHRONIZE

MICROSEQUENCER

PARALLEL IN

SERIAL OUT

SERIAL IN

PARALLEL OUT

RESULT LATCH

CONTROL

LOGIC

STATUS

DATA

DSI

DSO

DSCLK

SERIAL

CLOCK

RCV DATA LATCH

CPU

INSTRUCTION

COMMAND LATCH

DATA

DEVELOPMENT SYSTEM

BDM SER

COM BLOCK

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

SPMCK16Z4MPV20 Datasheet(PDF) 104 Page - Freescale Semiconductor, Inc

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