SPMCK16Z4MPV20 datasheet(183/500 Pages) FREESCALE

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M68HC16 Z SERIES

MASKED ROM MODULE

USER’S MANUAL

7-1

SECTION 7

MASKED ROM MODULE

The masked ROM module (MRM) is only available with the MC68HC16Z2 and the

MC68HC16Z3. The MRM consists of a fixed-location control register block and an 8-

Kbyte mask-programmed read-only memory array that can be mapped to any 8-Kbyte

boundary in the system memory map. The MRM can be programmed to insert wait

states to match slower external development memory. Access time depends upon the

number of wait states specified, but can be as fast as two clock cycles. The MRM can

be used for program accesses only, or for program and data accesses. Data can be

read in bytes, words or long words. The MRM can be configured to support system

bootstrap during reset.

7.1 MRM Register Block

There are three MRM control registers: the masked ROM module configuration regis-

ter (MRMCR), and the ROM array base address registers (ROMBAH and ROMBAL).

In addition, the MRM register block contains the signature registers (RSIGHI and

RSIGLO), and ROM bootstrap words (ROMBS[0:3]).

The module mapping bit (MM) in the SIM configuration register (SIMCR) defines the

most significant bit (ADDR23) of the IMB address for each M68HC16, M68CK16, and

M68CM16 Z-series module. Because ADDR[23:20] are driven to the same value as

ADDR19, MM must be set to one. If MM is cleared, IMB modules are inaccessible. For

more information about how the state of MM affects the system, refer to 5.2.1 Module

Mapping.

The MRM control register block consists of 32 bytes, but not all locations are imple-

mented. Unimplemented register addresses are read as zeros, and writes have no ef-

fect. Refer to D.4 Masked ROM Module for the register block address map and

7.2 MRM Array Address Mapping

Base address registers ROMBAH and ROMBAL are used to specify the ROM array

base address in the memory map. Although the base address loaded into ROMBAH

and ROMBAL during reset is mask-programmed as user-specified, these registers

can be written after reset to change the default array address if the base address lock

bit (LOCK in MRMCR) is not masked to a value of one.

NOTE

In the CPU16, ADDR[23:20] follow the logic state of ADDR19. The

MRM array must not be mapped to addresses $7FF000–$7FFFFF,

which are inaccessible to the CPU16. If mapped to these addresses,

the array remains inaccessible until a reset occurs, or it is remapped

outside of this range.

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