SPMCK16Z4MPV20 datasheet(180/500 Pages) FREESCALE

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STANDBY RAM MODULE

M68HC16 Z SERIES

6-2

USER’S MANUAL

6.2 SRAM Array Address Mapping

Base address registers RAMBAH and RAMBAL are used to specify the SRAM array

base address in the memory map. RAMBAH and RAMBAL can only be written while

the SRAM is in low-power stop mode (RAMMCR STOP = 1) and the base address lock

(RAMMCR RLCK = 0) is disabled. RLCK can be written once only to a value of one;

subsequent writes are ignored. This prevents accidental remapping of the array.

NOTE

In the CPU16, ADDR[23:20] follow the logic state of ADDR19. The

SRAM array must not be mapped to addresses $080000–$7FFFFF,

which are inaccessible to the CPU16. If mapped to these addresses,

the array remains inaccessible until a reset occurs, or it is remapped

outside of this range.

6.3 SRAM Array Address Space Type

The RASP[1:0] in RAMMCR determine the SRAM array address space type. The

SRAM module can respond to both program and data space accesses or to program

space accesses only. Because the CPU16 operates in supervisor mode only, RASP1

has no effect. Table 6-2 shows RASP[1:0] encodings.

Refer to 5.5.1.7 Function Codes for more information concerning address space

types and program/data space access. Refer to 4.6 Addressing Modes for more in-

formation on addressing modes.

6.4 Normal Access

The array can be accessed by byte, word, or long word. A byte or aligned word access

takes one bus cycle or two system clocks. A long word or misaligned word access re-

quires two bus cycles. Refer to 5.6 Bus Operation for more information concerning

access times.

6.5 Standby and Low-Power Stop Operation

Standby and low-power modes should not be confused. Standby mode maintains the

RAM array when the main MCU power supply is turned off. Low-power stop mode al-

lows the CPU16 to control MCU power consumption by disabling unused modules.

Relative voltage levels of the MCU VDD and VSTBY pins determine whether the SRAM

is in standby mode. SRAM circuitry switches to the standby power source when VDD

drops below specified limits. If specified standby supply voltage levels are maintained

during the transition, there is no loss of memory when switching occurs. The RAM ar-

ray cannot be accessed while the SRAM module is powered from VSTBY. If standby

operation is not desired, connect the VSTBY pin to VSS.

Table 6-2 SRAM Array Address Space Type

RASP[1:0]

Space

Program and data accesses

Program access only

Freescale Semiconductor, Inc.

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