SPMCK16Z4MPV20 datasheet(176/500 Pages) FREESCALE

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SYSTEM INTEGRATION MODULE

M68HC16 Z SERIES

5-70

USER’S MANUAL

However, the internal pull-up driver can be overcome by bus loading effects. To en-

sure a particular configuration out of reset, use an active device to put DATA0 in a

known state during reset.

The base address field in the boot chip-select base address register CSBARBT has a

reset value of all zeros, so that when the initial access to address $000000 is made,

an address match occurs, and the CSBOOT signal is asserted. The block size field in

CSBARBT has a reset value of 512 Kbytes. Table 5-26 shows CSBOOT reset values.

5.10 Parallel Input/Output Ports

Sixteen SIM pins can be configured for general-purpose discrete input and output. Al-

though these pins are organized into two ports, port E and port F, function assignment

is by individual pin. PE3 is not connected to a pin. PE3 returns zero when read and

writes have no effect. Pin assignment registers, data direction registers, and data reg-

isters are used to implement discrete I/O.

5.10.1 Pin Assignment Registers

Bits in the port E and port F pin assignment registers (PEPAR and PFPAR) control the

functions of the pins on each port. Any bit set to one defines the corresponding pin as

a bus control signal. Any bit cleared to zero defines the corresponding pin as an I/O

pin. PEPA3 returns one when read, and writes have no effect.

5.10.2 Data Direction Registers

Bits in the port E and port F data direction registers (DDRE and DDRF) control the di-

rection of the pin drivers when the pins are configured as I/O. Any bit in a register set

to one configures the corresponding pin as an output. Any bit in a register cleared to

zero configures the corresponding pin as an input. These registers can be read or writ-

ten at any time. DDE3 returns zero when read. Writes have no effect.

Table 5-26 CSBOOT Base and Option Register Reset Values

Fields

Reset Values

Base address

$000000

Block size

512 Kbyte

Async/sync mode

Asynchronous mode

Upper/lower byte

Both bytes

Read/write

AS/DS

DSACK

13 wait states

Address space

Supervisor space

IPL1

NOTES:

1. These fields are not used unless “Address space” is

set to CPU space.

Any level

Autovector

Interrupt vector externally

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